As different mixed-signal design applications require different configurations of SPICE netlist, RTL and behavioral models, flexibility in languages and topologies supported is crucial for a mixed-signal verification solution. In this video, you will learn about the evolution of Real Number Modeling, a type of behavioral modeling that models analog behavior in the digital domain using discretely simulated REAL values. We will discuss the differences between wreal modeling and SV nettype and some of the advantages that SV nettype brings to SoC design, including superior support for low power.
Arturo Salz, Scientist, Synopsys
Closing this window clears your chat history and ends your session. Are you sure you want to end this chat?
NOTICE: You are interacting with an AI-powered chatbot that provides general information about Synopsys, including its products and services, which may be incorrect or incomplete. In the event of any conflict or discrepancy, the terms of your applicable agreements supersede any information provided by this chatbot. These chats may be accessed by Synopsys and its service providers to customize the experience and improve this tool, and your use of this chatbot is an agreement to that data processing activity.