Cloud native EDA tools & pre-optimized hardware platforms
Well, our job is to route signals that typically require hand-crafting—for example, connections in analog and custom digital IP blocks. Our goal is to improve custom design productivity while still delivering extremely high quality of results (QoR).
The big difference between custom and digital routing is that the digital paradigm is well standardized, so digital routing requirements are easy to abstract into a general solution. This is less true for custom. For custom, even designers working at the same company, on the same node and on the same type of design might have different expectations for what the router should do.
Of course, digital designs can also include signals that need custom-style routing. So, the router we developed for Custom Compiler is also available in IC Compiler II to handle these signals.
There are many! For device-level routing, designers need the routing between certain signals to be closely matched, for example. They also have specific requirements for how connections to gates and source/drain regions are made, how local interconnect layers are used, whether special routing topologies are needed (for example, fishbone or backbone routing)—the list goes on. They even need stacked-layer routing for some technologies.
For block-to-block routing, designers want compact routing for bundled nets, connections with as few jogs and layer changes as possible, etc. Some connections require common path resistance to be minimized. Others require matched length routing, shielding, or differential-pair routing.
Our goal is to make it easy for users to get the results they want from the router. We apply the intelligence of our algorithms to handle connection details, so designers don’t need to do that themselves, while providing intuitive controls for driving decisions that impact QoR.
We call this approach “visually-assisted automation” (VAA). VAA uses the user interface paradigm most familiar to custom layout designers: graphical guidance and real-time visual feedback. Unlike competing tools, our router doesn’t rely on users writing complex scripts and constraints, pushing a button and then waiting to see what happens.
Our interactive router is my favorite example because we’ve done something quite new. Our starting point was a “follow-the-cursor” style router. The routing algorithm follows behind the user as they drag their mouse to provide a real-time DRC-correct connection. Doing this well is challenging. If you’re not careful, the solution can be quite jumpy—overreacting to even small mouse movements. We developed a fresh algorithm that provides a very stable solution. Our users love this feature because it provides nearly complete control but still significantly reduces layout effort.
Our pattern router is another significant innovation. We developed this to speed-up device-level routing. As I mentioned before, different designers can have very different ideas about what routing patterns they want. Our pattern router provides a graphical catalog of routing solutions that users can select from. They can click on one of the routing patterns in the catalog and see it implemented on canvas in real-time. If they don’t like it, they can pick a different one. This is extensible, so companies can define their own routing patterns if they want one we didn’t already include.
For block-to-block routing, our most important visually-assisted automation feature is our topology router and editor. Designers can use this to provide high-level guidance for the path they want our router to follow. We can propose a topology automatically, and layout designers can drag and drop waypoints to make changes as needed.
Yes. Reuse is a powerful way to improve analog productivity. We support this with our template-based design flow, which is a central feature of Custom Compiler. A layout done with Custom Compiler can be saved as a template to be reused later. Templates include circuit topology, placement patterns, dummies, guard rings, and routing—all based on the original design. This lets us regenerate a new layout following the same “spirit” as the original, even if device sizes, the number of devices, parameters, or even the design rules are different.
Although FinFET nodes introduced a lot of additional design rule complexity and added requirements like coloring and track pattern support, we’ve been handling these issues for several years. Our router is being used in production for 5-nanometer designs, and we’re already working on features for nodes below that.
To me, the technology trend that requires the most innovation from custom routing is advanced packaging and 3DIC. But this is a big topic—perhaps we can save it for another time.