Cloud native EDA tools & pre-optimized hardware platforms
2018 was a great year for a number of market segments, with strengths in 5G, AI, high-performance computing, and automotive. We expect them to be key industry drivers in 2019.
I agree. Last year we saw growth in semiconductor innovation with strong momentum into 2019. There was tremendous growth in the AI/ML sector. Growth of 5G and AR/VR in gaming and industrial sectors is creating interesting new opportunities. And autonomous technologies, for example, are driving the need for higher reliability. Of course, there are also other traditional sectors, too, like mobile, data center, and high-performance computing.
From our business view, significant trends and challenges we help address are related to power and reliability in 7nm and below process nodes, ultra-low voltages of operation, and multiphysics reliability issues in advanced packaging, such as 3DIC.
In addition, the transition to 5/3nm and beyond, as well as the low-voltage dynamics and yield robustness associated with them, has been a big jump and learning experience for customers. With respect to power rail analysis, more attention has been given to design robustness and reliability for an increasing number of companies, especially at lower nodes. Power integrity issues are increasingly included as a primary concern rather than an afterthought. This is a bigger concern as more companies are now exploring 3DIC designs.
The list of care-abouts from our collective customer base include:
· Power Integrity
· EM/IR signoff—this is becoming as challenging as timing signoff
· FinFET thermal and reliability issues
· Process variability
· Timing closure
· Margin management
· Power grid design challenges at 7nm:
– There’s a 5x increase in grid complexity, compared to 16nm. Power grids have 10B+ nodes
– 500mV—Ultra-low voltage computing means margins are razor thin, and variability is severe
– The need for increased power noise scenario coverage for greater signoff confidence to achieve the desired Fmax on silicon.
The design challenges resulting from EM/IR can no longer be addressed at the very end of the design cycle. EM/IR needs to be thoughtfully built into the design process right from the beginning. ‘Shifting Left’ is required to drive the right methods into the process. Our recent announcement with Fusion Compiler is a big part of that vision. Giving power to the block designer to not only analyze but also fix issues early in the design cycle at the block level before full-chip integration has provided significant productivity benefits.
Enabling RedHawk Analysis Fusion earlier in physical design flows helps designers achieve 5X increase in productivity and faster convergence during signoff with better QoR using ANSYS’ industry-standard power integrity and reliability analyses. Leveraging signoff-quality solutions during the in-design phase provides early visibility into design issues and allows them to be fixed up front. Specifically, new innovative placement, clock tree synthesis, and post-route IR-driven optimization strategies have enabled users to reduce manual work and maximize design robustness through IR recovery. Recently, designers were able to eliminate 95% of IR drop violations using RedHawk Analysis Fusion on a large graphics processor design.
In-design rail flow enabled by RedHawk Analysis Fusion allows the P&R engineering team to easily run the RedHawk engines under the hood and automatically deliver signoff-quality results back to IC Compiler II for fixing. This drives better decisions for achieving PPA goals early. Also, thermal reliability is a key concern in FinFET designs. By enabling self-heating analysis during in-design, physical design engineers can analyze and fix reliability issues earlier by doing thermal-aware EM checks.
We are excited about our progress and momentum addressing advanced-node needs with RedHawk-SC, built on ANSYS SeaScape, the world’s first custom-designed big data architecture for electronic system design and simulation. All of ANSYS’ 7nm customers are using RedHawk-SC for power integrity signoff with great feedback, and it is enabled for RedHawk Analysis Fusion for in-design IC Compiler II optimizations.
Great! As we deploy our new Fusion Design Platform, our customers are excited and look forward to achieving even better results with EM/IR integration into the flows.
Customers have given great feedback on the benefits this partnership provides, primarily in two areas. The first is the ease-of-use of in-design rail analysis that enables physical design block designers to do IR analysis work early and avoid surprises down the road. Secondly, the most important component is the IR-driven optimization opportunities we are giving customers using the industry signoff-quality data—including full automation beginning from placement. Customers have reported amazing results, as mentioned earlier, and we look forward to their continued success and being a part of that.
It has been an exciting journey collaborating at the engineering level with ANSYS, customers, and foundries, and it has produced great innovation and customer results.
I agree, we have seen our mutual customers benefit from this great relationship in driving faster schedules and building in a scalable model for best design robustness. In fact, our customers have taken this relationship a step further—they are driving initiatives and working closely with us on adjacent applications to further drive the benefits.