Synopsys Verification IP is architected to address the challenges of SoC verification and offers a broad portfolio of interface and memory VIP. Synopsys Verification IP, based on a native SystemVerilog UVM architecture, is simple to integrate into any SystemVerilog UVM testbench environment. To accelerate coverage closure, each VIP includes built-in verification plans, built-in functional coverage and sequence library source code. For improved debug, it is integrated with Synopsys’ unique protocol-aware debug environment, Verdi Protocol Analyzer, which gives users a high-level view of the protocol from which they can easily navigate through the protocol hierarchy from the high-level transactions and transfers to the low-level object field values.
Since the announcement of the native SystemVerilog architecture in 2012, the Synopsys Verification IP portfolio has rapidly expanded to encompass titles needed for SoC verification including on-chip buses and off-chip interfaces: AMBA® 4, AMBA 5 CHI, OCP 3.0, PCI Express (4.0 through 1.0), Ethernet (up to 100G), MIPI (multiple titles), HDMI, SATA, SAS, I2C, I2S, UART and USB. In addition to broad customer usage on a wide range of IPs and SoCs, the VIP is used and tested with DesignWare IP to simplify customers’ connectivity and integration testing.
The Synopsys VIP portfolio is being continually enhanced and expanded, most recently with the addition of the latest JEDEC memory standards to provide a complete solution for SoC verification and with the addition of test suites for block-level verification. In addition to this the portfolio has also been enhanced to include PCI Express 4.0, HDMI 2.0 and HDCP 2.2.