MIPI DSI provides a low-power, low-latency and low-cost chip-to-chip connectivity solution, linking multimedia processors to displays or other multimedia system-on-chips (SoCs). It targets a range of applications, including mobile (smartphones, tablets), automotive (advanced driver assistance systems (ADAS) such as infotainment), and multimedia (AR/VR). However, as demand moves towards high-resolution 4K displays, the specification’s bandwidth limitations become a challenge.
MIPI DSI operates on the MIPI D-PHY physical link at 2.5 Gbps per four lanes yielding a maximum data rate of 10 Gbps per link. However, as outlined below, high-end video and image resolutions such as 4K and 3D 1080p require higher bandwidth.
- 4K: 24-bit RGB @ 60 frames per second (FPS) requires 13 Gbps (12 Gbps for active area)
- 3D 1080p: 24-bit RGB @ 60 FPS requires 12 Gbps (11 Gbps for active area)
For deeper color modes, bandwidth requirements are even higher, creating a problem that would normally require designers to increase DSI data lanes by re-architecting devices and redesigning circuits, which results in higher design time, cost and risk. The VESA DSC incorporated into the MIPI DSI specification can help break through such bandwidth limitations without significantly changing the ASIC architecture and system circuits.