Cloud native EDA tools & pre-optimized hardware platforms
By: Pedro Ricardo Miguel, Sr. ASIC Digital Design Engineer, Synopsys
Displays for high-end smartphones, automotive infotainment systems, and augmented reality (AR)/ virtual reality (VR) devices are becoming more sophisticated with quad HD or 4K resolutions at faster frame rates and support for RGB formats. This evolution has introduced new challenges for designers – managing the required data bandwidth while reducing power consumption and without compromising visual quality. Designers need a protocol that enables visually lossless compression over display interfaces like MIPI® Display Serial interface (DSI®).
The Video Electronics Standards Association (VESA) Display Stream Compression (DSC) standard offers visually lossless performance and low latency for ultra-high-definition (UHD) displays. VESA has collaborated with the MIPI Alliance to get the DSC standard adopted into the MIPI DSI standard. This article describes the VESA DSC standard and highlights how the standard allows visually lossless data compression rates up to 4x, which designers can implement with an integrated MIPI DSI IP solution.
MIPI DSI provides a low-power, low-latency and low-cost chip-to-chip connectivity solution, linking multimedia processors to displays or other multimedia system-on-chips (SoCs). It targets a range of applications, including mobile (smartphones, tablets), automotive (advanced driver assistance systems (ADAS) such as infotainment), and multimedia (AR/VR). However, as demand moves towards high-resolution 4K displays, the specification’s bandwidth limitations become a challenge.
MIPI DSI operates on the MIPI D-PHY physical link at 2.5 Gbps per four lanes yielding a maximum data rate of 10 Gbps per link. However, as outlined below, high-end video and image resolutions such as 4K and 3D 1080p require higher bandwidth.
- 4K: 24-bit RGB @ 60 frames per second (FPS) requires 13 Gbps (12 Gbps for active area)
- 3D 1080p: 24-bit RGB @ 60 FPS requires 12 Gbps (11 Gbps for active area)
For deeper color modes, bandwidth requirements are even higher, creating a problem that would normally require designers to increase DSI data lanes by re-architecting devices and redesigning circuits, which results in higher design time, cost and risk. The VESA DSC incorporated into the MIPI DSI specification can help break through such bandwidth limitations without significantly changing the ASIC architecture and system circuits.
The collaboration between MIPI and VESA to incorporate DSC into DSI has provided “designers of source and display devices [with] a visually lossless, standardized way to transfer more pixel data over display links and to save memory size in embedded frame buffers in display driver ICs.” (VESA Display Stream Compression white paper, March 3, 2014). Figure 1 shows a block diagram of VESA DSC integrated into MIPI DSI.
Figure 1: An example of how DSC and DSI interoperate on host and device sides
The VESA DSC algorithm can compress data in constant bit rate mode, providing a deterministic size stream that can be transported by DSI without further processing or padding. By using a deterministically sized stream, all packet sizes are known, independent of the image color variation or other complexities.
Table 1 shows multiple compression rates with and without DSC. For example, a 24-bit RGB image normally transmits 24 bits per pixel (bpp), but with DSC, the bandwidth is compressed to 12 bpp, thus only needing to transmit half of the data rate – a 2:1 compression. For the same 24-bit RGB image, with DSC, data is compressed to 8 bpp, thus needing to transmit one third of the original amount of data – a 3:1 compression. The compressions do not compromise image quality as the DSC encoding is visually lossless.
Table 1: Sample compression rates with and without DSC
With VESA DSC, 4K and 3D 1080p video and image resolutions are now possible over existing display links.
- 4K, compressed to 12 bpp @ 60 FPS requires 6.5 Gbps – Possible with 3 or 4 lanes
- 4K, compressed to 8 bpp @ 60 FPS requires 4.4 Gbps – Possible with 2, 3 or 4 lanes
- 3D 1080p, compressed to 12 bpp @ 60 FPS requires 6 Gbps – Possible with 3 or 4 lanes
- 3D 1080p, compressed to 8 bpp @ 60 FPS requires 4 Gbps – Possible with 2, 3 or 4 lanes
Before compression, an image is divided into a grid of slices. Slices are always coded and decoded independently to ensure transmission errors aren’t propagated across the slices. A DSC encoder, which can be made up of multiple cores that operate in parallel, applies compression to each slice independently. Figure 2 shows an example of how DSC cores can compress an image efficiently. The DSC encoder in this example (on the left) includes four cores. A 4K image (on the left) is split into 4 columns by 15 rows, and each resulting slice is compressed by the corresponding DSC cores (indicated by color) in parallel.
Figure 2: An example of a 4K (3840x2160) resolution image divided into slices, to be compressed in parallel
Since DSC does not use inter-frame compression, it offers very low latency and reduced memory size, compared to other compression standards such as H.264 or H.265. DSC’s compression algorithm was designed to be implemented in hardware without the need for multimedia processors, making it highly efficient for area and power in SoCs. With the appropriate architecture, DSC decoders can process 3 pixels per clock cycle to reduce the clock frequency requirements, which is ideal for newer technologies like chip-to-glass liquid-crystal displays (LCDs).
VESA rigorously tests their algorithm to assess the image quality in selected parameters. A selected group of volunteers, unfamiliar with the image compression technology but with good vision, are individually presented an application that periodically alternates between original and decompressed images, including photography, text and artificial patterns generated by computer. The task is to try to detect any loss of quality by identifying any flickering artifacts. The results are then tabulated to determine the mean score from which VESA classifies compression as visually lossless or not.
Visually lossless compression is the ideal method to enable quad HD or 4K resolution embedded displays in high-end smart phones, automotive infotainment systems and AR/VR devices. The limited bandwidth in today’s display links is keeping designers from meeting the required data transmission for 4K or even 3D 1080p image and video resolutions. The VESA DSC standard helps designers overcome such limitations without costly and risky circuit redesign. VESA DSC is an emerging standard that delivers visually lossless compression, providing designers flexible, low-latency, low-memory, and error-resilient results.
Synopsys has integrated VESA DSC into its silicon-proven DesignWare® MIPI DSI IP to enable quad HD or 4K resolution displays. The IP, together with the DesignWare MIPI D-PHY IP, provides designers with a complete, interoperable display solution for integration into application processors. The integrated IP reduces memory size and data transmission bandwidth to lower power consumption and electromagnetic interferences.