To meet the low-power, performance and functionality demands of advanced electronics products, virtually every SoC designed today is a multicore SoC. In this environment, on-chip cache memory plays a critical role, as memory architecture is fundamental in determining system performance.
Historically, CPU speed has outpaced memory speed. This performance gap led to the use of on-chip cache memory in single-processor systems to prevent the CPU from having to wait for instructions and data from memory. However, in a multicore SoC, individual cores must access and share data across the entire chip.
While cache control protocols were once implemented as flexible software implementations, the performance requirements of multi-block multi-threaded ICs have moved these into on-chip hardware implementations.
To address the issue of maintaining cache coherency in today's multicore chips, ARM® created the ARM® AMBA® ACE™ (AXI Coherency Extensions) and a number of interconnect implementations that use AXI4™ and ACE to deploy hardware-based cache coherency. Building on the ACE specification, ARM more recently released AMBA 5 CHI (coherent hub interface), a packet-based protocol developed to provide high-performance, cache-coherent communication between ARM Cortex®-A50 series processors. It is used with other ARM AMBA protocols to create cache-coherent SoC interconnects that encompass memory subsystems, signal processing, graphics processing and off-chip communication.
The AMBA 5 CHI enables users to ensure cache-coherent interconnects, yet there are always challenges in verifying a SoC through its various stages of design from interconnect, to RTL integration, to full SoC verification. Verification IP is a key element in meeting those challenges; however, the current generation of verification IP (VIP) is running out of steam to provide the performance, productivity and features to verify the design as RTL is incrementally integrated into the system.
Fortunately, next-generation SystemVerilog™ VIP enables the rapid creation of a multi-protocol verification environment for an AMBA-based SoC including CHI, ACE-Lite™ and other AMBA interfaces. It offers stimulus, system-wide data integrity checking, performance analysis, performance checking, protocol-aware debug and coverage closure.