Selecting Standard Cell and Memory IP to Meet Chip Goals
By Rob Raghavan, director of marketing for the DesignWare Embedded Memory, Logic Library and Memory Test and Repair products, Synopsys
Designers must make practical trade-offs in performance, power consumption and die area, or PPA, in virtually every SoC implementation today. Rob Raghavan, product marketing director for embedded memories and logic libraries at Synopsys, explains how the Synopsys’ DesignWare® Duet Packages of Embedded Memories and Logic Libraries provide design teams all of the fundamental IP elements needed to strike the best combination of performance, power and area in their system-on-chip (SoC) implementations.
It’s becoming increasingly important for design teams to choose the right embedded memory and logic library IP for their SoC designs. This is especially true for mobile and consumer markets where products are developed using a combination of application processors, memories, communications protocols and other logic to deliver data and multimedia content. This high-performance functionality must work seamlessly together in a single integrated device and operate with the lowest possible power consumption to preserve battery life − all at a cost that is economical enough for the consumer market.