Selecting Standard Cell and Memory IP to Meet Chip Goals

Selecting IP

SoCs are becoming increasingly complex as more design blocks are integrated to achieve differentiation and greater functionality. As foundational IP elements in any chip design, standard cell libraries and embedded memories must give designers a versatile set of options to optimize the performance, power and area of each block, as well as the full SoC. While designers need flexibility in their memory and logic IP, the selection of which cells and memory instances to use can be daunting due to the large number of memory compiler and logic library variants available.

The DesignWare Duet Packages of Embedded Memories and Logic Libraries offer optimized combinations of high-performance and high-density SRAMs, register files, ROMs, standard cells, datapath libraries and Power Optimization Kits. Options for overdrive/low voltage, process, voltage, temperature corners (PVTs), high-density SRAMs and multi-channel logic standard cells are also available, enabling designers to achieve the best combination of performance, power and area for their specific applications. To improve yield and reduce test and silicon costs, the DesignWare Duet Packages with STAR Memory System® include embedded memory test and repair, providing a comprehensive solution of power- and performance-optimized embedded memories and logic libraries with automated memory test, repair and diagnostic capabilities.

The Embedded Memory, Test and Logic Portfolio

Embedded Memory

The amount of memory embedded in advanced SoCs has been steadily increasing for years. The DesignWare Memory Compiler portfolio, which includes single-, dual- and two-port SRAMs, ROMs and register files, support a wide range of process technologies from 250nm to 28nm. These memory compilers are available in high-speed, high-density and ultra high-density architectures and support advanced power management techniques including fine-grained power gating, selective use of HVt, and long L devices, and level shifters. Support for ultra low-voltage operation and dual rail for Dynamic Voltage Frequency Scaling (DVFS) can deliver up to 30% lower standby power. For power-sensitive mobile applications, designers can take advantage of source biasing and multiple power management modes, including Light Sleep, Deep Sleep and Shut Down to significantly reduce leakage and dynamic power dissipation. Ultra high-density two-port SRAM and 16 Mbit single-port SRAM compilers deliver further area and leakage power reductions. As a result, DesignWare Embedded Memories can deliver maximum frequency with the lowest possible power.

Embedded Test and Repair

The DesignWare STAR Memory System provides integrated test, repair and diagnostics to support repairable or non-repairable embedded memories for any foundry or process node. Its performance-optimized architecture combined with automated hierarchical test and repair logic insertion and integration capability gives designers ease-of-use and increased productivity in achieving their performance, power, area and test goals. The system’s processor includes a BIST module to execute test algorithms that can be modified in the RTL or modified in silicon through the programmable capability in the BIST module. A built-in self-diagnosis module determines the location of any memory defect and provides error logging by scanning out failure data for silicon debug. When testing redundant memories that have failures, a built-in repair and redundancy allocation module identifies available redundant elements and determines the optimum redundancy configuration. The reconfiguration data module translates redundancy allocation into a memory-specific repair signature. With the STAR Memory System, designers can improve manufacturing test quality and silicon yield without sacrificing performance. In addition, advanced transient error fault tolerance enables SoC designers to efficiently address high field-reliability and safety requirements for mission-critical applications.

Logic Libraries

The DesignWare Logic Libraries portfolio includes yield-optimized standard cells for a wide range of manufacturing processes from 180nm to 28nm process nodes. The standard cell libraries are offered in multiple architectures to enable designers to optimize circuits for performance, power and area: a high-speed 12 track library targeting high-performance design requirements, a high-density nine track library offering balanced PPA for general purpose logic at 65nm and larger, and an ultra high-density seven track library that delivers a 30 percent area improvement while reducing dynamic power consumption by 20 percent, compared to conventional standard cell products. The libraries also include multiple voltage threshold implants (VTs) and support multiple channel gate lengths to minimize leakage power at 40nm and below.

For designs requiring extremely low power while maintaining superior performance, designers can use Power Optimization Kits (POKs), a set of specially designed cells with power switches and level shifters. The POKs make it possible to shut down parts of a design to save power or to dynamically operate functional blocks at multiple voltages to achieve the best tradeoffs between dynamic power consumption and performance in multiple operating modes. Cost-effective design changes are possible with the Engineering Change Order (ECO) Kits, which enable metal-only changes for last minute product requirements or to correct final verification issues.

Everything Needed to Implement Advanced SoCs

The DesignWare Duet Packages of Embedded Memories and Logic Libraries offer an integrated portfolio of standard cell libraries, memory compilers and embedded test and repair capability. With a unique cell architecture and optimum mix of cell and memory types, the Duet Packages enable designers to achieve both high performance and low power for their entire SoC, while keeping area requirements to a minimum. Energy efficiency and area efficiency without compromising performance: it’s the right combination.