SoCs are becoming increasingly complex as more design blocks are integrated to achieve differentiation and greater functionality. As foundational IP elements in any chip design, standard cell libraries and embedded memories must give designers a versatile set of options to optimize the performance, power and area of each block, as well as the full SoC. While designers need flexibility in their memory and logic IP, the selection of which cells and memory instances to use can be daunting due to the large number of memory compiler and logic library variants available.
The DesignWare Duet Packages of Embedded Memories and Logic Libraries offer optimized combinations of high-performance and high-density SRAMs, register files, ROMs, standard cells, datapath libraries and Power Optimization Kits. Options for overdrive/low voltage, process, voltage, temperature corners (PVTs), high-density SRAMs and multi-channel logic standard cells are also available, enabling designers to achieve the best combination of performance, power and area for their specific applications. To improve yield and reduce test and silicon costs, the DesignWare Duet Packages with STAR Memory System® include embedded memory test and repair, providing a comprehensive solution of power- and performance-optimized embedded memories and logic libraries with automated memory test, repair and diagnostic capabilities.