CRC is an error detection scheme that is well suited to serial data streams, but its overhead has generally left it unused for parallel data – such as the received and de-serialized PCI Express packets in a PCI Express controller.
One fairly simple technique for error detection, which lends itself well to such parallel data, is parity protection (Figure 2). One parity bit is appended to the datapath for each n bits (usually 8) of actual data, such that the total count of ones in the binary field is either even or odd – depending on the variation chosen. For example, in an 8-bit even parity system, the parity bit for the value 255 (1111_1111 in binary) is 0 – as there are 8 ones in the binary representation of 255. In that same system, the parity bit for the value 254 (1111_1110 in binary) would be 1, as there are only 7 ones in the binary representation of 254, so an additional is needed in the parity to make the total count even. (As a historical note, back in parallel bus days, even parity was preferred because the pull-up resistors common to many busses meant an undriven bus would be read as 1111_1111 with parity 1, for 9 ones and thus an even parity error.)