RAS Data Protection Considerations for PCI Express Designs
By Richard Solomon, Technical Marketing Manager, Synopsys
The PCI Express® protocol includes a robust set of Reliability, Availability, Serviceability (RAS) features, but it is up to the SoC designer to ensure this protection is maintained throughout the SoC. For the past few years, most design teams have considered the bus itself to be the primary source of data transmission errors. However, with the advent of teen-nanometer FinFET processes and the migration of enterprise-grade storage to direct-attach PCI Express, more and more attention is turning to on-chip data protection.