The IBIS-AMI modeling and simulation framework has enabled system and hardware engineers to verify off-chip interconnect designs by running simulations in an accurate yet efficient manner. Over time, the IBIS-AMI modeling process has been simplified with a variety of EDA vendors now providing add-ons to their existing simulator portfolio. An IBIS-AMI test bench offers a simple and fast way to ensure SerDes interoperability and link performance benchmarking.
Today’s PAM-4 112G PHY uses ADC-based flexible DSP architecture instead of a process, voltage, temperature (PVT)-dependent and hard-to-scale analog architecture. This architectural shift has significant implications on simulation and modeling of high-speed SerDes transceivers.
Figure 1 shows a typical 112G serial link implemented in a DSP-based receiver architecture. It consists of a transmitter (TX) with some finite-impulse response equalization (FIR) and a dispersive channel. The channel output is sent to a receiver composing an analog front-end (AFE), ADC, and a DSP block, which includes a feed-forward equalizer (FFE), a decision-feedback equalizer (DFE), clock and rate recovery (CDR), and an adaptation block (ADAPT). In such a design, a significant portion of the signal equalization comes after the ADC within the DSP.