Modern systems-on-chips (SoC) are becoming more complex with a larger number of CPUs and advanced GPUs to support a wide range of applications with additional peripheral masters and slaves to meet the market demands. In any SoC-based subsystem, masters are broadly classified as latency-sensitive masters (e.g., CPUs), bandwidth-sensitive masters (e.g., GPUs) and best-effort masters (e.g., SATA and USB interfaces). These masters communicate with a shared memory controller (DDR) slave device.
In a SoC-based on-chip communication systems, the masters communicate with different slaves through the interconnect fabric. The interconnect plays a vital role in routing traffic between the masters and slaves. The access time to the bus (i.e., the time until the bus is granted) for latency-sensitive masters (CPU) and bandwidth requirements for bandwidth-sensitive masters (GPU) are key factors in determining the overall performance in a SoC, while accessing a shared memory controller slave.
AMBA® AXI™ is a high-performance SoC bus protocol. Synopsys’ DesignWare® IP for AMBA Interconnect (DW_axi) is an interconnect fabric implementation of AMBA 3 AXI/AMBA 4 AXI protocol. The DW_axi supports different arbitration schemes while routing the traffic between masters and slaves. These arbitration schemes are used to distribute the bandwidth and control the latency requirements of the masters. However, these arbitration schemes are not enough to meet requirements of the masters.
The AMBA 4 AXI protocol brings in quality of service (QoS) signaling on the AXI bus to address the challenges imposed by bandwidth and latency requirements of various IP in a SoC.
By using the QoS feature, the average bandwidth requirements of different masters can be met by distributing the slave’s bandwidth amongst the masters in a fair mechanism to improve the SoC’s performance. The QoS feature also helps designs meet the average latency requirements of latency-sensitive masters.