Modern systems-on-chips (SoC) are becoming more complex with a larger number of CPUs and advanced GPUs to support a wide range of applications with additional peripheral managers and subordinates to meet the market demands. In any SoC-based subsystem, managers are broadly classified as latency-sensitive managers (e.g., CPUs), bandwidth-sensitive managers (e.g., GPUs) and best-effort managers (e.g., SATA and USB interfaces). These managers communicate with a shared memory controller (DDR) subordinate device.
In a SoC-based on-chip communication systems, the managers communicate with different subordinates through the interconnect fabric. The interconnect plays a vital role in routing traffic between the managers and subordinates. The access time to the bus (i.e., the time until the bus is granted) for latency-sensitive managers (CPU) and bandwidth requirements for bandwidth-sensitive managers (GPU) are key factors in determining the overall performance in a SoC, while accessing a shared memory controller subordinate.
AMBA® AXI™ is a high-performance SoC bus protocol. Synopsys’ DesignWare® IP for AMBA Interconnect (DW_axi) is an interconnect fabric implementation of AMBA 3 AXI/AMBA 4 AXI protocol. The DW_axi supports different arbitration schemes while routing the traffic between managers and subordinates. These arbitration schemes are used to distribute the bandwidth and control the latency requirements of the managers. However, these arbitration schemes are not enough to meet requirements of the managers.
The AMBA 4 AXI protocol brings in quality of service (QoS) signaling on the AXI bus to address the challenges imposed by bandwidth and latency requirements of various IP in a SoC.
By using the QoS feature, the average bandwidth requirements of different managers can be met by distributing the subordinate’s bandwidth amongst the managers in a fair mechanism to improve the SoC’s performance. The QoS feature also helps designs meet the average latency requirements of latency-sensitive managers.