Is a FinFET Process the Right Choice for Your Next SoC?
By Prasad Saggurti, Product Marketing Manager, Synopsys
The continuous shrinking of planar CMOS processes to allow for greater density reduces area but also results in increased leakage power, which makes the shift to smaller planar processes less attractive. An alternative that many designers are considering are FinFETs, but moving from planar to FinFET is not a straight forward choice. There are several factors one must consider when making the decision about whether or not to move.
Let’s first look at how FinFETs differ from planar CMOS technology. In CMOS, a single gate controls the source-drain channel. In planar processes, the gate does not have good control of the channel, with leakage currents between source and drain even when the gate is off. By contrast, in FinFET transistors the channel is a thin vertical fin with the gate fully wrapped around three sides of the channel. This results in much better control of a highly depleted channel, and thus lower leakage.