DesignWare Technical Bulletin

Is a FinFET Process the Right Choice for Your Next SoC?

By Prasad Saggurti, Product Marketing Manager, Synopsys 

The continuous shrinking of planar CMOS processes to allow for greater density reduces area but also results in increased leakage power, which makes the shift to smaller planar processes less attractive. An alternative that many designers are considering are FinFETs, but moving from planar to FinFET is not a straight forward choice. There are several factors one must consider when making the decision about whether or not to move.

Let’s first look at how FinFETs differ from planar CMOS technology. In CMOS, a single gate controls the source-drain channel. In planar processes, the gate does not have good control of the channel, with leakage currents between source and drain even when the gate is off. By contrast, in FinFET transistors the channel is a thin vertical fin with the gate fully wrapped around three sides of the channel. This results in much better control of a highly depleted channel, and thus lower leakage.

FinFETs offer other benefits over planar as well. For example, in planar technologies, as we went from 250 nanometer (nm) down to 65-, 40-, and 28-nm, we saw leakage going up, resulting in an increase in total power. But we observe a dramatic drop in leakage when going from planar to FinFETs. Additionally, while going to smaller geometries typically results in increased variability, FinFETs actually lower variability, enabling operation at low voltages.

For all the benefits they offer, FinFETs do also present some design constraints. For one thing, the effective transistor sizes that you can use in a FinFET process is quantized, so it's not as granular as in a planar technology and, as a result, designing a balanced circuit is challenging.

Lack of body biasing is another drawback: a lot of chip designers used back biasing to reduce leakage or even forward biasing to temporarily boost performance at the cost of leakage, but with FinFETs this method of controlling your device and circuit behavior is not available.

In addition, parasitics are higher, not only because of the smaller geometries but simply as the result of the way in which FinFETs are manufactured. The gate caps are higher and so this is something that we need to keep an eye on. Finally, while aging positive bias temperature instability (PBTI) in FinFETs is not a problem, negative bias temperature instability (NBTI) is a real issue and affects performance.

The good news is these are considerations at the circuit design level and are generally addressed by the vendor supplying a variety of IP including memories and libraries, analog IP and PHYs. Chip designers typically do not need to worry about these design challenges unless they are designing custom circuitry.

Having looked at specific benefits and challenges of designing in FinFET processes, let’s use the PPARCY framework when considering a move to FinFET technology. The framework on which to base the decision to move to a FinFET process is comprised of Performance, Power, Area, Readiness of the process, Cost and Yield.

Performance (PPARCY)

If the process not only meets your goals, but enables you to exceed your design requirements, it gives you the flexibility to implement more capabilities or accomplish your performance goals with reduced area and power. With FinFETs you can observe, on average, a performance improvement of 30% when moving from a 28-nm planar to a 16-nm or 14-nm FinFET process. With Synopsys’ libraries, for example, when comparing the 12.5-track library at 28-nm to the 16-nm 9-track library, even the 9-track library exceeds the performance of the 12.5-track from 28-nm, demonstrating a tremendous increase in speed.

Power (PPARCY)

You’ll also see significant improvements in power consumption. Contrary to the increased leakage one would expect with the lowering of threshold voltages, the leakage power is half that of the previous planar process. Dynamic power has also come down along with the nominal voltage, however dynamic power is now the bottleneck to achieving lower power. To reduce dynamic power, we must operate at a lower voltage, which in turn, makes the static noise margin of the SRAM bitcells worse. Synopsys has enabled lower voltage operation by using application-appropriate assist circuitry.


Area savings are modest when moving to FinFET. With planar technologies, it used to be that just moving to the next geometry was enough to give a 50% reduction in area. However, the move from 40-nm to 28-nm didn’t result in such large area savings. Typical area savings when going from 28-nm planar to 16-nm FinFET are around 35% to 40%. Improvements a little bit above 40% are possible by trading off performance.

Readiness of the Process (PPARCY)

Another important consideration is whether the technology is proven—have others already made the switch and how reliable is the technology? With customers taping out now and getting ready for volume production on FinFET processes from leading foundries, it’s not a risky choice to use one of the many FinFET process for your next design. In addition, from an IP standpoint, Synopsys has built and taped out test chips with embedded memories and logic libraries, as well as interface IP on FinFET processes from these foundries. Silicon results validate the improved performance and power results on these nodes.


There is greater manufacturing complexity with FinFETs, resulting in much higher manufacturing costs as compared to planar; this increased cost is not offset even with a 50% area reduction, so area savings alone wouldn’t justify a move to FinFET; rather this transition has to be based on the ability to deliver something that was not possible without this technology move, be it better performance, lower leakage and/or longer battery life.

Yield (PPARCY)

Processes are stabilizing at much faster rates than at earlier nodes. However the failure mechanisms in FinFETs are different from the failures observed in planar processes so running the same BIST algorithms that are used for planar technologies will not be effective for FinFETs. In its memory BIST solution, Synopsys has added new algorithms to catch FinFET-specific faults, while at the same time adding column and row redundancy to the memories to capture multiple word line failures to improve overall yield.


So, looking at all the PPARCY criteria, moving to FinFET makes sense for high volume products in which the area reduction would justify the increased cost of the FinFET. High-margin products also justify a switch to FinFET because the extreme power reduction and performance increase are valued in these products and the higher cost will be recouped in the cost of the finished product. Server CPU, discrete GPU, bitcoin mining, high-performance computing and enterprise networking are key market segments that are driving the adoption of FinFET processes, as they are the ones where the PPA improvements have the greatest value. Fundamentally the decision to move or not comes down to whether it makes sense from an economic standpoint.