FinFETs offer other benefits over planar as well. For example, in planar technologies, as we went from 250 nanometer (nm) down to 65-, 40-, and 28-nm, we saw leakage going up, resulting in an increase in total power. But we observe a dramatic drop in leakage when going from planar to FinFETs. Additionally, while going to smaller geometries typically results in increased variability, FinFETs actually lower variability, enabling operation at low voltages.
For all the benefits they offer, FinFETs do also present some design constraints. For one thing, the effective transistor sizes that you can use in a FinFET process is quantized, so it's not as granular as in a planar technology and, as a result, designing a balanced circuit is challenging.
Lack of body biasing is another drawback: a lot of chip designers used back biasing to reduce leakage or even forward biasing to temporarily boost performance at the cost of leakage, but with FinFETs this method of controlling your device and circuit behavior is not available.
In addition, parasitics are higher, not only because of the smaller geometries but simply as the result of the way in which FinFETs are manufactured. The gate caps are higher and so this is something that we need to keep an eye on. Finally, while aging positive bias temperature instability (PBTI) in FinFETs is not a problem, negative bias temperature instability (NBTI) is a real issue and affects performance.
The good news is these are considerations at the circuit design level and are generally addressed by the vendor supplying a variety of IP including memories and libraries, analog IP and PHYs. Chip designers typically do not need to worry about these design challenges unless they are designing custom circuitry.
Having looked at specific benefits and challenges of designing in FinFET processes, let’s use the PPARCY framework when considering a move to FinFET technology. The framework on which to base the decision to move to a FinFET process is comprised of Performance, Power, Area, Readiness of the process, Cost and Yield.