Embedded Memory Test & Repair at 20-nm Nodes and Below
By Sandeep Kaushik, Sr. Product Marketing Manager, Synopsys, Inc.
With embedded memories dominating the SoC area in today’s designs, SoC yield relies heavily on memory yield. In order to meet the stringent requirements of next-generation, high-performance devices, these designs must be larger and use multiple processor cores. The increased design complexity presents a unique set of test and yield challenges including higher test costs, yield implications due to a higher total bit count, higher power consumption during test, and lower design productivity. Additionally, there is greater manufacturing complexity in 20-nm technology nodes, which create new yield challenges, both in the form of increased defect densities and in the form of new types of failure mechanisms that need to be modeled for accurate detection, diagnosis, and repair. It is essential to have an embedded memory test and repair solution that not only meets the above challenges for today’s designs, especially those at 20-nm and below, but that is also cost-effective.
This article provides an overview of the newly released DesignWare® STAR Memory System® 5 to specifically address the challenges of designs on 20-nm and below technologies.