DesignWare Technical Bulletin

Optimized for efficient hardware implementation, the DesignWare Foundation Cores floating point library consists of RTL and bit-accurate C++ models of mathematical and floating point components. With the robust library of components, designers can build custom floating point designs and make power, performance and area trade-offs to meet their design requirements. Using a variety of floating point formats gives designers the ability to adjust the dynamic range and precision of their design and to try different implementations to reduce their design’s power consumption. Another method to meet design requirements is using the flexible floating point format to build floating point designs.

The Flexible Floating Point Format

To reduce redundant logic, allow sharing of operations, and give designers more control of their designs, the FFP format was created. The FFP format consists of three sections: The status flags, the exponent, and the significand. The status flags are provided to carry information about the value of the floating point number that can be used in the hardware design. Current status indicators include:

• zero - The number is zero
• infinity - The number is infinity
• invalid - The number is NaN or invalid
• inexact - The significand has been truncated in an operation (previous or present) and information was lost
• 1scmpl - The significand in one’s complement form
• sign - Carries the sign of zero or infinity numbers in the FFP system

The exponent is the signed integer value in two’s complement, and the significand is the fixed-point true-and-complement value in the form of “sx.xxxxxxx” where “s” is the sign bit. This new format simplifies the calculations. Status information is transferred from one operation to another, and can reduce the critical path. With the elimination of normalization of the significand at each stage of an operation, the amount of redundant logic can be reduced. In addition, designers can control the precision at each FFP operation to control design accuracy at each stage.

Algorithmic Simulations with Bit-Accurate C++ Models

When tuning the accuracy of a design, designers need to try various precisions in different stages of calculations or to implement completely different algorithms to validate their implementation. To enable designers to quickly test their algorithms, bit-accurate C++ models are included with the DesignWare Foundation Cores floating point library. These C++ models are generated based on the configured RTL, or the hardware configuration set by the designer.

The designer interfaces with the top level of the DesignWare Foundation Cores C++ model. The top level has two main functions: it allows the designer to define if the interface is going to use a SC_MODULE construct or a plain C++ class interface, and it makes the data type conversions needed to call the core portion of the C++ model. The C++ models are generic and can be run in any C++ environment. A C++ test bench with random vector generator is also included with the configured model.

IP-Based Floating Point Design

Sub-functions are a critical component of floating point operations, such as the floating point adder shown in Figure 2.

A typical floating point component includes the significand calculation (alignment, fixed-point addition, normalization, and rounding), the exponent calculation, and finally the re-packaging of the calculated number. When implementing only one operation, each stage is required for the calculation. If however, a combination of operations can eliminate redundant logic from the first stage.

When the calculation is completed, a simple converter component is used to convert to the IEEE 754 format for easy software integration, as shown in Figure 3.

Implementation of Floating Point Networks with DesignWare Foundation Cores

When designing with the DesignWare Foundation Cores FFP IP, designers can control the precision of their design. Designers can use the fused component DW_fp_dp2 from the Synopsys DesignWare library, or build from atomic floating point components (two multipliers and one adder).

At the atomic level, designers need blocks to convert the inputs from standard FP representation to FFP representation. The DWFC_fp_fp2ffp component converts a floating point number to the flexible floating point format and the DWFC_fp_ffp2fp component converts to standard floating point.

To illustrate how to control the precision of the first pair of values in a floating point number, each converter indicates the input FP format as ‘f’ significand bits and ‘e’ exponent bits. The second pair indicates the size of the significand and exponent fields of the output FFP format. The first operation on FFP values is performed by the FFP multiplier. It gets two operands in the FFP format (f+2,e) and generates an output in the FFP format (f+8,e+1). These values can be adjusted via configuration to generate larger or smaller formats. Once the multiplier generates the result (which is not necessarily normalized), the addition is done to obtain the result in the FFP system. Once again, the FFP formats used for the inputs and outputs of the FFP adder can be different (Figure 4). The final block performs conversion back to the IEEE FP system. At this level, normalization and rounding are applied.

The design shown in Figure 5 is one possible implementation that can be built with the DesignWare Foundation Cores components. Another implementation would be to use the DWFC_fp_ffp_mult component. With this component, the converter from standard floating point to flexible floating point is not used. This enables further reduction in the area and delay in the design’s implementation. With the library of components, designers can select the implementation that best meets their design goals.

Tuning the Design

To build a two-term dot-product floating point component that is slightly smaller than other implementations, designers can adjust the precision of their components while maintaining approximately the same precision based on the parameters, as shown in Table 1.

If the accuracy from this baseline needs to be increased, designers can add additional bits into the significand or exponent fields at the different stages of the network. Once they have generated a new set of components, they can quickly simulate the design using the generated bit-accurate C++ Models to tune the accuracy of the design to meet project specific requirements.

The Design Environment

Using a project approach, designers create a library of custom components for their design. As each component is configured, the RTL and C models are installed into a project directory, which includes all of the files associated with the verification and implementation of the components (Figure 6). Once the design is completed, the files can be integrated into the larger SoC design and designers can continue to refine their RTL for the next generation of the product.

Summary

The DesignWare Foundation Cores gives designers power and control to meet the design requirements of their floating point designs. With the ability to explore design space with different configurations, and implementations to make accuracy, power, performance and area trade-offs by tuning their design to have the precision needed. Designers can also share operations and customize the circuit. With the C++ models designers can quickly run simulations on the generated models to ensure that their design meets project requirements.