When designing with the DesignWare Foundation Cores FFP IP, designers can control the precision of their design. Designers can use the fused component DW_fp_dp2 from the Synopsys DesignWare library, or build from atomic floating point components (two multipliers and one adder).
At the atomic level, designers need blocks to convert the inputs from standard FP representation to FFP representation. The DWFC_fp_fp2ffp component converts a floating point number to the flexible floating point format and the DWFC_fp_ffp2fp component converts to standard floating point.
To illustrate how to control the precision of the first pair of values in a floating point number, each converter indicates the input FP format as ‘f’ significand bits and ‘e’ exponent bits. The second pair indicates the size of the significand and exponent fields of the output FFP format. The first operation on FFP values is performed by the FFP multiplier. It gets two operands in the FFP format (f+2,e) and generates an output in the FFP format (f+8,e+1). These values can be adjusted via configuration to generate larger or smaller formats. Once the multiplier generates the result (which is not necessarily normalized), the addition is done to obtain the result in the FFP system. Once again, the FFP formats used for the inputs and outputs of the FFP adder can be different (Figure 4). The final block performs conversion back to the IEEE FP system. At this level, normalization and rounding are applied.