Tightly-Coupled Analog and DSP Architecture for Best 112G SerDes IP Performance

Manu Verma, Product Marketing Manager, Synopsys


Hyperscale data centers are going through a paradigm shift with the advent of technologies like Artificial Intelligence (AI) and Edge Compute. Trends such as 5G for AI-powered IoT edge applications, huge amount of data for video streaming, and zettabytes of data for fully autonomous vehicles, have required hyperscale data centers to support exponential growth of data volume and distributed low-latency processing. In addition, integration of hardware accelerators and deep learning functions in hyperscale data centers are using higher bandwidth at higher power. All of this is creating the need for SerDes architectures that can provide higher throughput with lower power consumption while reducing overall system cost. 

This article highlights the benefits of the 112G SerDes IP that implements an analog and digital architecture to deliver maximum performance and reach in 400G/800G hyperscale data center system-on-chips (SoCs).

Hyperscale Data Centers Are Evolving

As per Cisco's Global Cloud Index, hyperscale data centers will grow rapidly and in 2021 around 53% of all up and running data centers will be hyperscale data centers. This volume of network traffic demands an increase in bandwidth to 400G, enabled by 112G Ethernet PHY which is now emerging as the interconnect of choice whether for short-reach or long-reach configurations, utilizing copper or optical cable. In the last six years, Ethernet speeds have gone from 25G/50G to 400G today and are expected to go to 800G soon. Switches, which are an integral part of a hyperscale data center, are supporting bandwidth from 12.8 Terabits per second (Tb/s) to 25.6 Tb/s today and to 51.2 Tb/s expected in the next couple of years. As switches shift to 51.2 Tb/s, they will need 512 SerDes lanes each running at 100 Gb/s. This will be a combination of Very Short Reach (VSR), Medium Reach (MR), and Long Reach (LR) SerDes. Hence, to meet the system requirement, a 112G SerDes needs to provide optimized performance across VSR, MR, and LR interfaces. As shown in Figure 1, hyperscale data centers are evolving to handle increasing Ethernet speeds and switch bandwidth, as well as changes in module type.

Hyperscale data center architecture evolving to handle higher data rates and bandwidth

Figure 1: Hyperscale data center architecture evolving to handle higher data rates and bandwidth

Optimal SerDes Architecture

Real world operation of a SerDes in a hyperscale data center is very demanding and requires robust performance in very challenging conditions such as multitude of channel insertion loss, extreme temperature cycles, different types of packages with different trace lengths and discontinuities, etc. Hence, meeting interference tolerance (ITOL) and jitter tolerance (JTOL) compliance is not enough.

A 112G SerDes PHY architecture with the right mix of analog and digital blocks is the most optimized implementation for best performance, lowest power and smallest area. For instance, analog blocks can help digital blocks with signal pre-conditioning which can unburden the DSP, significantly reducing power and providing robust bit error rate (BER) performance. Similarly, digital blocks can help analog blocks compensate for linearity and other analog impairments across process, voltage, and temperature variations.

There are more essential features a 112 SerDes IP can offer that go beyond power, performance, and area. They are adaptive adaptation and temperature tracking, which further optimize performance in real world scenarios.

Optimum Adaptation for Superior Performance Across VSR to LR with no External Intervention

  • Adaptive adaptation: Running the adaptation in multiple passes achieves an optimized configuration. The current pass results are monitored and used to adjust the adaptation targets of the next pass. The PHY starts as a generic LR PHY but self-adapts to the best configuration suitable for a given reach.

  • Continuous time linear equalization (CTLE) with additional boost amplifier/suppressor: The dynamic range of CTLE boost is an important consideration for operation across the channel loss profile. Unwanted boost in CTLE, while operating in a low loss channel, is equally as challenging as deficient boost at high loss. Implementing CTLE, having additional boost amplifier/suppressor circuits, extends the dynamic range. This increases boost for long channels and reduces unwanted boost for short channels, thus implementing true VSR to LR operation.

  • Sampling point optimization: The digital block can fine-tune performance over a wide range of channels by adjusting the clock sampling. The clock-path sampling point can be tweaked with respect to datapath sampling point, significantly improving the performance of mixed reach operation from VSR to LR.

  • Dynamic analog-to-digital (ADC) resolution: Analog blocks can adjust ADC resolution by shutting down additional comparisons that are not required in low-resolution modes. This provides optimal power savings and channel reach.

  • Flexible performance knobs: For short low-loss channel, the power consumption can be further reduced by disabling floating front-end equalization (FFE) taps, utilizing fewer ADC conversions and reducing analog front-end (AFE) bias current and bandwidth.

Temperature Tracking Ensuring Robust Performance Across PVT Variations

The analog performance changes due to temperature variations. For applications that need to operate over a wide temperature range, with high-speed serial link functioning all the time without re-start or re-adaptation, it is critical that the link receiver includes continuous adaptive equalization to compensate for change in channel parameters due to temperature variations. Below are some of the features that ensure optimized 112G performance across temperature variations:

  • Temperature-aware continuous calibration and adaptation (CCA): Optimizing calibration and adaptation algorithms and implementing them intelligently to achieve adaptation only occurs when there is a change in temperature. This prevents channel performance from degrading. An internal temperature sensor, for on-die temperature measurements can be used to trigger certain adaptations, like CTLE, only when there is a specific temperature change. Other adaptations (like receiver FFE, DFE, etc.) are enabled periodically to track any change that occurs in between.

  • True positive/negative full range temperature tracking: Monitor and track temperature across the entire range, as shown in Figure 2, such that the PHY can be powered at any intermediate temperature while performing at a high level at increasing or decreasing temperatures from -40°C to 125°C.

Figure 2: Full range temperature tracking


The exponential increase in data traffic demands hyperscale data centers to support higher bandwidths enabled by 112G SerDes IP which is becoming the interconnect of choice. A balanced analog and digital architecture is required for 112G SerDes to ensure optimized performance in terms of signal losses, cross talks, higher throughput and lower power. The combination of analog and digital blocks with right calibration and adaptation algorithms provides best-in-class performance across process, voltage, and temperature.  

Synopsys DesignWare® 112G Ethernet PHY IP, available in advanced FinFET processes including 5nm, with an ADC and DSP architecture supports power scaling techniques for significant power reduction in low-loss channels. The PHY’s optimized layout maximizes bandwidth per die-edge through stacking and placement on all 4 edges of the die. Its unique architecture supports independent, per lane data rates for ultimate flexibility. Most recently, the silicon-proof of DesignWare 112G Ethernet PHY IP in 5nm process demonstrated zero BER post forward-error correction in greater than 40dB channels while offering power-efficiency of less than five picojoules per bit (pJ/bit).