Real world operation of a SerDes in a hyperscale data center is very demanding and requires robust performance in very challenging conditions such as multitude of channel insertion loss, extreme temperature cycles, different types of packages with different trace lengths and discontinuities, etc. Hence, meeting interference tolerance (ITOL) and jitter tolerance (JTOL) compliance is not enough.
A 112G SerDes PHY architecture with the right mix of analog and digital blocks is the most optimized implementation for best performance, lowest power and smallest area. For instance, analog blocks can help digital blocks with signal pre-conditioning which can unburden the DSP, significantly reducing power and providing robust bit error rate (BER) performance. Similarly, digital blocks can help analog blocks compensate for linearity and other analog impairments across process, voltage, and temperature variations.
There are more essential features a 112 SerDes IP can offer that go beyond power, performance, and area. They are adaptive adaptation and temperature tracking, which further optimize performance in real world scenarios.