Leveraging the basic subsystem concepts above, Synopsys has developed an IP subsystem targeting the fast-growing IoT edge device market – specifically addressing “always-on” applications requiring a robust level of DSP performance to process functions such as complex sensor fusion, voice and gesture recognition, image detection and audio playback while adhering to the constrained power envelope of a battery operated device.
The DesignWare Smart Data Fusion IP Subsystem (Figure 4) is designed to efficiently process data from numerous digital and analog sensors, either as the main processing element in an MCU, or as an offload engine for the host processor in a larger SoC. The fully configurable IP subsystem includes an ARC EM5D, EM7D, EM9D or EM11D processor. This family of low-power cores combines RISC and DSP instructions and hardware to manage the extensive processing required by advanced data fusion algorithms and to improve performance for a range of audio formats including MP3, SBC, OPUS and AAC LC.
The subsystem's integrated microDMA controller enables memory and peripheral access during processor sleep modes. In addition, the subsystem incorporates highly-optimized I/O peripherals including multiple SPI, I2C and analog-to-digital converter interfaces, further lowering gate count and energy consumption.
To ease software development, the subsystem includes software drivers and a rich library of off-the-shelf DSP functions supporting filtering, correlation, matrix/vector, decimation/interpolation and complex math operations. Designers can implement these sensor-specific DSP functions in hardware using a combination of native DSP instructions and tightly coupled hardware accelerators to boost performance efficiency and reduce power consumption.
Additionally, Synopsys' embARC Open Software Platform gives software developers online access to a comprehensive suite of free and open-source software that accelerates code development for the subsystem.