When designing for high reliability, NVM architects must ensure that their testing procedures cover all of the following:
- Characterization: Ensure that the NVM IP is manufacturable in high volumes.
- Qualification: Ensure that the NVM IP meets all appropriate industry standards.
- Reliability: Ensure that the NVM IP meets the target reliability specifications.
Passing qualification can give a false sense of security when it comes to meeting end product reliability targets. For example, qualification testing 1,000 NVM arrays with zero failures demonstrates a failure rate of just over 2,000 parts per million (ppm) with a confidence level of 90%. That is not acceptable for most volume products and is nowhere near the requirements of automotive-grade products. Typically, automotive OEMs will look for a failure rate of 1 ppm or fewer.
The answer to this challenge is additional extended reliability testing. By collecting additional statistics, Synopsys can make accurate reliability projections that meet the needs of automotive OEMs, Tier 1 and Tier 2 suppliers by using more detailed measurements from test chips. Extended reliability testing is the most often overlooked component when it comes to demonstrating a high-reliability NVM array. Extended reliability testing focuses on “tail bits,” which behave differently from the overall population and, if ignored, are more likely to cause reliability issues in the field.
Synopsys collects extensive data for analysis to estimate the probability that a bitcell will fail. It then uses that data within a model that predicts NVM behavior over longer periods of time.
Using the reliability trends of a limited number of samples, Synopsys has created an empirical model to evaluate the long-term reliability of a much larger sample size. Table 1 shows the accuracy of an empirical model of reliability versus the design architectural choices.