Cloud native EDA tools & pre-optimized hardware platforms
Manuel Mota, Product Marketing Manager, Synopsys
The fifth generation of cellular mobile communications – 5G – has arrived, and promises virtually unlimited data throughput, game changing new applications and use cases (Figure 1). The 5G vision is proving to be a potent driver for continued technological innovations in the semiconductor industry. The different pieces of the complex puzzle leading to full deployment and adoption of 5G are starting to fall into place. The Analog Front-End (AFE) and the RF architectures are just some of the pieces that must significantly evolve to enable 5G. This article discusses the main technical requirements determined by the 3rd Generation Partnership Project (3GPP) for 5G and how the AFE has evolved to meet such requirements.
Figure 1: How 5G meets the requirements of a wide range of use scenarios
5G represents a significant departure from existing cellular communication protocols. The promised tens of gigabits per second throughput can only be achieved by making use of larger quantities of RF spectrum in a more efficient way.
3GPP has adopted several strategies to enable the amount of bandwidth necessary for 5G:
It is known that lower frequencies suffer lower attenuation over the air and have better ability to penetrate obstacles, like walls, than higher frequencies. The LTE frequency range (600 MHz up to ~6 GHz) continues to be a good compromise for previous generations of cellular protocols as it enables cells with reasonable reach and coverage inside buildings. However, this spectrum is crowded and very fragmented: LTE bands seldom contain contiguous spectrum in excess of few tens of MHz, making it challenging to free high-bandwidth channels required for 5G.
For these bands (otherwise known as FR1), 3GPP has defined a maximum channel bandwidth of 100 MHz and implements intra- and inter-band carrier aggregation to allocate broader spectrum to a given connection.
Additionally, the coordinated use of relatively wide and unlicensed bands (the industrial, scientific and medical, or ISM radio bands) available worldwide like the 5 GHz band, standardized in later releases of LTE, is carried out to 5G. It is also expected that additional bands at ~6 GHz will be allocated to 5G.
However, increases in bandwidth will only be achieved by taking advantage of the less crowded mmWave frequency range. At frequencies between ~24 GHz and 100 GHz, there are portions of spectrum, up to several GHz wide, that are being considered for 5G use (Figure 2).
Figure 2: The 5G spectrum, which includes FR1 and FR2 bands
For the mmWave bands (also called FR2), 3GPP has defined a maximum channel bandwidth of 400 MHz and implements carrier aggregation to further expand spectrum allocated to a given connection.
mmWave propagation is challenging due to the high attenuation and impossibility to cross obstacles such as walls or even people. This leads to the need to densify the network, with the deployment of a heterogeneous network infrastructure that includes a multitude of small, pico, and femtocells to supplement the shorter range macro cells both outdoors and indoors.
In addition, beam-forming (with massive MIMO architectures and relying on artificial intelligence (AI) for better steering) is used to focus beam energy on the best path to the user, avoiding obstacles, and increasing reach all while supporting multiple users sharing the same spectrum.
5G achieves a more efficient use of the allocated RF spectrum by supporting spatial diversity with MIMO antenna arrays and higher modulation indexes (up to 256 quadrature amplitude modulation (QAM) both for uplink and downlink streams in release 16).
Due to the challenges of deploying 5G networks, 3GPP has defined a non-standalone (NSA) mode of operation where the 5G connectivity coexists with LTE and relies on the LTE infrastructure for the control path.
In NSA mode, the LTE infrastructure provides a fall back data path for connectivity in areas where 5G coverage is insufficient. This reduces the risks of the initial deployment and avoids the need to commission a large number of new cell sites required to achieve reasonable 5G coverage, especially in the mmWave bands.
It is expected that most initial 5G deployments will focus on the sub-6 GHz (FR1) bands, with mmWave FR2 bands expected soon after.
5G FR1 frequency bands are mostly repurposed LTE bands. They can leverage similar RF modulation / demodulation architectures, relying on similar AFE characteristics, even if the channel bandwidth has significantly increased with respect to LTE.
Very high-speed (operating at multi-giga-samples per second (GSPS)) analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) with high-resolution and low-power are now becoming available for SoC integration. Such data converters support the channel bandwidth available in mmWave bands and open the doors for the generalization of RF architectures that potentially reduce the complexity of the RF circuitry by moving the digital/analog divide closer to the antenna.
Traditional RF modulation/demodulation architectures are based on two concepts: Heterodyne (or IF) conversion and Zero-IF (or direct) conversion. These concepts alleviate the requirements on the ADC and DAC speed by adding complexity to the RF circuitry. Both rely on filtering and bringing down the selected relatively narrow bands to a frequency suitable to be processed by a low-speed data converter.
In heterodyne (or IF) conversion architectures, the band of interest is isolated with steep band-pass filters and then mixed down to a suitable low frequency, where it can be sampled by an ADC. Final complex, or real, down-conversion and decimation can be carried out in the digital domain (Figure 3).
Careful frequency mapping ensures that non-linear and mixing artifacts are out of band and effectively filtered out at different stages of the RF architecture. Unfortunately, due to the many filter requirements, this is costly from a complexity and power point of view, for most applications.
 For simplicity, all the examples shown refer to the Receive / down convert path. However, the Transmit / up convert path relies on similar concepts, although in symmetrical direction.
Figure 3: Heterodyne (or IF) conversion architecture block diagram
The alternative, Zero-IF (or direct) conversion architectures have been used in most modern wireless communication systems for LTE, WiFi, etc., due to their efficiency and reliability. In this case, the suitably filtered band of interest is mixed down to DC in quadrature. Two matching ADCs are used to convert complex IQ signals to the digital domain (Figure 4). Such architecture relaxes the low-pass filter characteristics at input of ADC, but some complications arise from potential limitations to image rejection due to IQ path imbalances and Local Oscillator (LO) frequency injection as well as the presence of in-band spurious.
Figure 4: Zero-IF (or direct) conversion architecture block diagram
Recent developments in the data converter technology are paving the way for direct RF sampling architectures that can process large swaths of RF spectrum directly by the ADC into the digital domain. (Figure 5). Such architectures avoid any mixing and therefore remove most of the frequency mapping issues. The architectures require very high-speed and broadband ADCs, and since channel selection is performed on the digital domain and the ability to implement gain in the analog domain is limited, they expose the ADC noise contribution to the system, leading to more stringent performance requirements.
By simplifying the RF circuitry and moving most of the data processing to the digital domain, direct RF sampling architectures gives flexibility to the channel selection process and future proof the system by supporting Software-Defined Radio (SDR) type of implementations.
Advances in integrated low-power data converter technology make the direct RF sampling architectures very promising for power- and cost-efficient 5G implementations, both at the macro cell and user device.
Figure 5: Direct RF sampling architecture block diagram
The main driver for the adoption of very high-speed data converters for 5G communications is the need to support RF channel bandwidth of up to 100 MHz or even 400 MHz. In addition, it is desirable to simultaneously process multiple channels or the complete 5G band, that spans up to several hundred MHz or GHz, to reduce the number of TX/RX chains and allow channel selection and carrier aggregation to be implemented in the digital domain.
The sampling theory mandates that the complete frequency band of interest is contained in the same Nyquist region that spans half of the sampling frequency to avoid aliasing effects. Realistically, a margin for a reasonable anti-alias filtering implementation must be factored in, further reducing the usable band (75% to 80% of Nyquist region is usually acceptable).
Therefore, data converter sampling rates in the order of 1 to 3 GSPS are desired. The high maximum sampling rate enables higher flexibility for frequency mapping optimization and simpler anti-alias filters, regardless of the applied RF modulation/demodulation architecture.
Data Converter performance requirements, in the context of 5G applications, is a function of the selected RF modulation/demodulation architecture and the depth of the QAM modulation and peak-to-average power ratio (PAPR) of the implemented signal.
Heterodyne and zero-IF architectures assume channel selection is carried out in the RF and analog baseband domains by a chain of amplifiers and accurate band-pass or low-pass filters.
This chain has the benefit of simplifying the requirements of the data converter:
The results relative impact of the ADC to the overall performance of the chain should be small. Conversely, for the same expected system performance, the ADC performance may be less aggressive.
On the other hand, direct-RF sampling architectures can be more demanding for the ADC performance. These architectures remove channel selection filtering from the analog domain (simpler band selection and anti-alias filtering are still implemented). As a result, larger sections of the RF spectrum are present at the input of ADC, ensuing the need for a higher back-off to avoid saturation coming from the higher signal levels in unwanted portions of the spectrum. To keep the ADC contribution to the NF of the chain at acceptable levels, the front-end broadband Low Noise Amplifier (LNA) gain must be kept high.
Given all the tradeoffs discussed, 12-bit resolution converters are adequate for any of these architectures, even for the highest QAM256 signal modulation level.
Given the number of antennas and bands that need to be supported, as well as the huge number of devices needed to achieve adequate coverage, 5G transceivers must take full advantage of integration to reduce power dissipation and costs.
Integrated 5G AFEs support multiple transmit and receive path, up to the total MIMO configuration. A typical implementation that supports an 8x8 MIMO in a mixed digital beam forming arrangement includes 8 transmit DACs and 8 receive ADCs. In addition, 5G AFEs may require additional ADCs for the observation channel. Figure 6 shows an AFE implementation example.
Figure 6: Example of a 5G Analog front-end implementing 4 TX and RX paths and observation channel
Given that the AFE processes signals that have very wide bands, the complete analog path of the signals from package to the ADC and DAC must be integrated into the AFE design. Special care must take place to minimize parasitics at package, IO pad, and ESD protection levels to limit the impacts on the AFE performance level. A well designed AFE IP integrates the complete analog signal path and ESD protections up to the IO pads and is properly terminated to eliminate difficult signal reflections that can jeopardize the operation of the transceiver.
For testability purposes the AFE should include extended control and visibility access to internal blocks, including analog loopback modes to facilitate automation of the production test.
Synopsys’ data converter portfolio offers an integrated AFE solution and includes:
Synopsys’ ADC is a low-power interleaved successive-approximation-register (SAR)-based architecture that integrates its own reference generation (no external components required) and its own high bandwidth, high impedance input buffer, termination resistors, ESD protection structures, and IO bumps for flip chip package implementations.
The ADC is fully contained and implements its own calibration circuitry to calibrate the spectral artifacts due to interleaving. This advanced calibration algorithm does not impose any limitation on the frequency content of the signals being processed.
The ADC is deployed with different number of interleaved lanes for optimal area usage in applications that require lower maximum sampling rate.
The Synopsys DAC is a current steering architecture implementing a calibrated NMOS current source matrix supporting NRZ and mix operating modes to deliver signal synthesis in the 1st and 2nd Nyquist bands. It integrates its own calibration circuitry and optional resistive loads to simplify the external circuitry and reduce BOM. The Synopsys DAC includes ESD protection structures and IO bumps for flip chip implementations.
Given the very broadband nature of the signals being driven to and from the AFE, a lot of attention must be paid to ensure couplings through package or PCB do not degrade the signal, impacting system performance. Package substrate and PCB design should be validated through simulations. For this purpose, Synopsys delivers specific views and models for signal and power integrity validation during the design phase to ensure that the complete system is correctly designed and delivers the expected performance.
Web page: Data Converter IP Solutions