To address the challenges of achieving the required system throughput, meeting the timing budget and supporting selected 25G Ethernet features, designers need a flexible solution that includes a complete subsystem including the media access controller (MAC), physical coding sublayer (PCS), and serializer/deserializer (SerDes).
Supporting data rates from 1G to 100G, the DesignWare Enterprise Ethernet MAC IP is designed for three different system level configurations: MAC only, MAC with the memory controller, and a complete direct memory access (DMA) with the ARM® AXI Interface. With a native 128-bit FIFO interface for minimal latency, jumbo frame support and a range of application-specific configurations, designers can easily integrate the application-tailored MAC into their design.
The DMA interface is included to ease the migration of 10G designs to 25G designs as the first generation of mass-deployed 10G designs often use the ARM AMBA on-chip interconnect. To facilitate this migration from 10G to 25G Ethernet, the DesignWare Enterprise MAC’s optional AMBA AXI interface can support 128-bit data transfers with up to 16 transmit and receive channels.
The MAC has a separate DMA channel in the transmit path for each queue in the MAC transaction layer (MTL) - Single or multiple DMA channels for any number of queues in MTL Receive path, and individual programmable burst size for Tx DMA and Rx DMA engines for optimal host bus utilization. Some of the main configurable options in the descriptor include:
- Byte-aligned addressing
- Dual-buffer descriptor ring and support for 64-bit addressing
- Descriptor architecture to allow large blocks of data transfer with minimum CPU intervention
- TCP Segmentation Offload (TSO) and IEEE 1588 Timestamps
- One-step PTP time correction in Tx
- Option to provide 64-bit Timestamp for received packets
- Option to give up to two VLAN tags in descriptor for insertion or replacement in Tx and stripped VLAN tags in Rx
- Option to split the packet header (layer 3 and layer 4) and layer 4 payload in different buffers
- Delivers RSS hash information for packets received with TCP/UDP over IP payload
The DesignWare Enterprise MAC is easily integrated with the Synopsys PCS layer. The PCS is configurable for a range of connectivity and provides support for both IEEE and consortium specifications for 25G Ethernet. Some of the key optional modules include the Read Solomon Forward Error Correction (RS-FEC) block defined by Clause 74 or Clause 91 of the IEEE 802.3 specification, link training support, and auto-negotiation. The PCS supports multiple interfaces including single 25G, 2x25G for 50G Ethernet, and 4x25G for 100G Ethernet. Details on the different configuration options are included in Synopsys coreConsultant.
The Enterprise MAC and PCS integrates seamlessly with the DesignWare Multi-Protocol 25G PHY IP. The PHY delivers outstanding signal integrity and jitter performance for data center applications and is extremely low in area and power with support for Energy Efficient Ethernet (EEE). The configurable transmitter and receiver equalizers enable customers to control and optimize signal integrity and at-speed performance, and the continuous calibration and adaptation (CCA) provides robust performance across voltage and frequency variations.
With Synopsys’ multi-protocol 25G PHY, all the components needed for a 25G Ethernet solution are available and fully tested to ensure designers can easily integrate the subsystem solution into their design, or as components of their design. With the PHY, designers can accomplish challenging tasks such as full subsystem simulation, synthesizing the subsystem with several different target libraries, timing closure, and placement and routing. Synopsys provides the implementation and verification scripts for easy subsystem configuration of their target applications.