ARC Processor Summit 2016

When: Tuesday, September 13th, 2016
Where: Santa Clara Marriott, 2700 Mission College Boulevard, Santa Clara, CA 95054

As embedded systems become more complex and integrate greater functionality, SoC developers are faced with the paradox of developing more powerful yet more energy-efficient devices. For the processors at the heart of these applications, performance efficiency is paramount.

Join us at Synopsys' ARC® Processor Summit to learn about the latest technologies and trends in embedded processor IP, software, programming tools and applications. This free one-day event will consist of multiple tracks in which experts from Synopsys, partners and the ARC user community will discuss challenges and solutions for IoT security, automotive safety, embedded vision and much, much more.

If you are involved in the development of hardware or software for SoCs or embedded systems, the ARC Summit is an event you won’t want to miss.

Time Description
9:00–9:30 Check-in and Breakfast
9:30–9:45 Opening Remarks
9:45–10:40 Keynote Address: IoT Standards Wars: Designers Caught in the Middle?
Linley Gwennap, The Linley Group
10:40–11:00 Break
  Hardware Track Software Track Embedded Vision Track
11:00–11:30  Addressing the Evolving Processing Needs of IoT Applications Zephyr: Creating a Best-of-Breed, Secure RTOS for IoT Advanced Vision Capabilities for Next-Generation SoCs
11:30–12:00 Optimizing Memory in IoT and Embedded Applications
12:00–12:30 APEX: Using ARC Processor Custom Extensions to Differentiate your SoC Using a Qualified Compiler to Develop Safety-Critical Software
12:30–1:30 Lunch and Demos
1:30–2:00 IoT Security: Protecting Your SoC from Malicious Physical and Software Attacks Sensor Processing for Smart Home and IoT Embedded Vision: Where We Are and Where We’re Going
2:00–2:30 Using the MPU with an RTOS to Enhance System Safety and Security
2:30–3:00 Maximizing Embedded Performance with Multicore Processors Software Development Kits for Simplifying Security Implementation The Vision API Landscape
3:00–3:30 Break
3:30–4:00 Designing with Processors in Safety-Critical Automotive Applications A Lightweight Trusted Execution Environment for IoT Edge Devices Using the OpenCL C Kernel Language for Embedded Vision Processors (3:30-4:15)
4:00–4:30 Pervasive Authentication for IoT: ARC Processors with PUFs (4:00PM)
4:30–5:00 Achieving 7X Better Power Efficiency with a Unique Sub-Threshold Technology Implementation of an ARC EM5D Processor Based Subsystem Embedded Natural Language Voice Interfaces Visual Perception and Computer Vision for Surveillance and Automotive (4:15 - 5:00)
5:00–5:30 Designing a Next-Generation PCI Express-Based Enterprise SSD Solution Using ARC Processors The Case for Trace Targeting CNNs for Embedded Platforms
5:30–7:00 Networking and Demos

9:40 AM – 10:35 AM
Keynote Address: IoT Standards Wars: Designers Caught in the Middle?
Linley Gwennap, Principal Analyst, The Linley Group

The Internet of Things is not a single market but rather a plethora of things, each with its own technology requirements and target customer. As a result, many new standards are being proposed, but these standards may meet the needs of only certain types of IoT devices. This presentation will discuss standards for communication protocols, software, and services for IoT devices, helping to sort out which are applicable and which are most likely to succeed. It will also address technologies for securing the IoT and other trends affecting SoC design.

Hardware Track

11:00 AM – 12:00 PM
Addressing the Evolving Processing Needs of IoT Applications
Rich Collins, Product Marketing Manager, Synopsys
Masami Nakajima, Ph.D., Core Technology Business Division, Renesas Electronics Corporation 

As IoT device implementations mature, in addition to meeting the integration and low-power demands of battery operated IoT applications, designers are looking to address the increasing processing needs of these applications. Sensor fusion has evolved into the broader scope of data fusion, where voice recognition, audio playback, face detection and basic gesture recognition complement the sensor processing functions on an IoT device. Ensuring secure operation and transmission of data is also critical for IoT devices supporting fitness and health applications, financial transactions and e-government products. Efficient processors and pre-verified, SoC-ready subsystems simplify the development of chips targeting ever more complex IoT applications with dedicated features addressing the evolving security and processing needs of these new IoT devices.

To manage this onslaught of new functionality, IoT edge devices increasingly require higher bandwidth analysis to be performed locally (on-chip). Synopsys and Renesas have worked together to build a new reference design supporting power efficient data fusion processing with higher performance MONOS embedded flash technology to provide the ideal power/performance trade-offs required for the next generation of IoT devices.

12:00 PM – 12:30 PM
APEX: Using ARC Processor Custom Extensions to Differentiate Your SoC
Joep Boonstra, Sr. Staff Architect, Synopsys

In a highly competitive semiconductor market, it is increasingly important to be able to quickly and easily differentiate your device. This session will introduce ARC Processor EXtension (APEX) technology, which can be used to extend the instructions and register set of the CPU as well as add tightly coupled peripherals and custom interfaces to the core. It will also include real-world examples and recent additions to optimize performance for complex extensions while retaining a simplified interface.

12:30 PM – 1:30 PM

1:30 PM - 2:30 PM
IoT Security: Protecting Your SoC from Malicious Physical and Software Attacks
Ruud Derwig, Software and Systems Architect, Synopsys 

Security is of critical importance to IoT applications. This session will present threats to IoT security, and hardware-rooted processor security solutions that defend against these. Both logical (software) as well as physical (hardware) attacks will be addressed. Special attention will be given to countermeasures for Side Channel Analysis (SCA) attacks, or non-invasive physical attacks that reconstruct secret cryptography keys from information leaked from an SoC’s power consumption or electromagnetic radiation. Without countermeasures, it can be surprisingly easy to obtain these secret keys, and therefore SCA countermeasures are required by more and more IoT standards.

2:30 PM - 3:00 PM
Maximizing Embedded Performance with Multicore Processors
Kulbhushan Kalra, Manager, ASIC Digital Design, Synopsys

The availability of specialized high-performance processors that support multicore implementation is changing high-end embedded applications. With limitations on maximum clock frequencies and power consumption, multicore processors are making it possible to address advanced applications with significant increases in performance and a minimal increase in power consumption. Processors designed for multicore implementation also support the variety of needs that arise in embedded applications and enable easy upgrade to higher performance for future designs. This presentation details the architecture of a processor family that has been designed specifically to address the requirements of high-performance, multicore embedded applications.

3:30 PM - 4:30 PM
Designing with Processors in Safety-Critical Automotive Applications
Fergus Casey, Senior R&D Manager, Synopsys 

As more SoC designs are used in electronic systems deployed in safety-critical applications, functional safety is an important consideration in system architecture and verification methodology. Security is also a key concern for connected cars and should be a consideration in safety applications. This session will outline the key requirements for ISO 26262 and security as they relate to processor IP and demonstrate how safety-critical IP and SoC developments can be greatly accelerated through the use of out-of-the-box safety ready IP, together with advanced verification qualification tools and methodologies.

4:30 PM - 5:00 PM
Achieving 7X Better Power Efficiency with a Unique Sub-Threshold Technology Implementation of an ARC EM5D Processor Based Subsystem
Uzi Zangi, CEO & Co-founder, PLSense 

The emerging Internet-Of-Things (IoT) market is causing the focus of IC design flows to shift from increasing performance to reducing power in order to meet the demands of battery operated devices to increase their battery lifetime.

PLSense has developed comprehensive technology for sub-threshold libraries and design flows, which enables the design of ICs that can operate at voltages as low as 0.45V while significantly improving battery life compared to existing solutions. As part of this technology, PLSense implemented an MCU chip fabricated on the TSMC 40-nm ULP process using Synopsys’ DesignWare® Smart Data Fusion IP Subsystem. This presentation will describe the implementation of the MCU using the sub-threshold technology and show how it achieved up to 7X better power per MHz than comparable solutions.

5:00 PM - 5:30 PM
Designing a Next-Generation PCI Express-Based Enterprise SSD Solution using ARC Processors 
Liang Chen, Chief Engineer, Digital Verification, Starblaze

High performance, small form factor and low power consumption are important considerations in the design and selection of an SSD product. Enterprise SSD products are also characterized by a very high “mean time between failures” (MTBF) value, high data integrity and end-to-end data protection. Enterprise SSD products are expected to be used in heavy workload environments and still deliver high performance. This presentation addresses the challenges and requirements for the underlying CPU in an Enterprise SSD solution. It highlights how a multi-core ARC HS Processor and ARC EM Processor based SoC proves to be the ideal choice for the Enterprise SSD product, and explains how ARC processors can easily meet key Enterprise SSD application requirements.

Software Track

11:00 AM - 11:30 AM
Zephyr: Creating a Best-of-Breed, Secure RTOS for IoT
Kate Stewart, Sr. Director of Strategic Programs, Linux Foundation 

Zephyr is a new upstream open source project for places where Linux is too big to fit. The starting point for Zephyr is from a commercial project that has been made open for the community to evolve and enhance into a secure best-of-breed RTOS for the IoT ecosystem. This talk will provide an overview of how we are incorporating leading technologies into the code base, and building up the community to support multiple architectures and development environments.

11:30 AM - 12:00 PM
Optimizing Memory in IoT and Embedded Applications
Francois Bedard, Sr. R&D Manager, Operating Systems and Open Source Software, Synopsys 

IoT edge devices need to provide required performance at ultra-low power and low cost to enable ubiquitous deployment. Both SoC silicon area and memory usage must be minimized to reduced overall system cost. In this session you will learn how to deploy an embARC-based IoT edge application software stack in a fraction of the memory required.

12:00 PM - 12:30 PM
Using a Qualified Compiler to Develop Safety-Critical Software
Mitesh Shah, Manager, Software Engineering, Synopsys 

The MetaWare Compiler has been qualified for use as the compilation toolchain when developing safety-critical applications according to ISO 26262. It can be used for components with a maximum Automotive Safety Integrity Level ASIL D. This session will describe how to use the compiler and the accompanying documentation in order to be in compliance with these important safety standards.

12:30 PM - 1:30 PM

1:30 PM - 2:00 PM
Sensor Processing for Smart Home and IoT
Dave Karlin, VP of Strategy, Hillcrest Labs 

Many emerging applications, such as virtual reality, augmented reality, and robotics have unique sensor processing requirements and require an optimum combination of hardware and software. This presentation will focus on how Hillcrest Labs’ specialized software and Synopsys’ ARC processors can enable high-accuracy, low-power sensor processing for Smart Home and a wide range of IoT applications.

2:00 PM - 2:30 PM
Using the MPU with an RTOS to Enhance System Safety and Security
Steve Ridley, Principal Software Engineer, Wittenstein 

For safety-critical software, it is necessary to understand the requirements of the application, be able to demonstrate that the requirements have been met and prove that all the code is necessary and tested. This disciplined approach to engineering is the starting point for safety applications. Run time monitoring of an application and its underlying hardware is also commonplace. One hardware peripheral that can help with this is a Memory Protection Unit (MPU). Correct configuration of the MPU can allow software bugs or corruption to be trapped before damage can occur; however, active management of the MPU in conjunction with an RTOS allows meaningful task/thread isolation of mission critical parts of the application. This presentation discusses methods of achieving partitioning and error detection using the MPU.

2:30 PM - 3:00 PM
Software Development Kits for Simplifying Security Implementation
Mike Borza, Member of Technical Staff, Security IP, Synopsys 

Secure Boot can greatly enhance the security of an embedded system by verifying that the code being loaded and executed has not been unknowingly or maliciously modified. This presentation will cover the Secure Boot Software Development Kit, which allows developers to implement Secure Boot systems using software-only constructs or with Synopsys offload engines. It will also provide an overview of Synopsys cryptography software, which includes a comprehensive suite of widely used crypto algorithms and simple plug-in modules to transparently support hardware acceleration or offload.

3:30 PM - 4:00 PM
A Lightweight Trusted Execution Environment for IoT Edge Devices
Ruud Derwig, Software and Systems Architect, Synopsys 

Developing completely bug-free software is complex and costly, but the bugs that remain pose a security threat when maliciously exploited. In addition, software in a device comes from sources with different trust levels: internal development, external suppliers, open source, and maybe even end-users. The standard solution for mixed-criticality components is isolation. For security this means a securely shielded Trusted Execution Environment. For low power/cost IoT edge devices, however, a separate secure processor or full virtualization is not an option. This session presents a lightweight solution to efficiently shield secure from non-secure software on a single microcontroller.

4:00 PM - 4:30 PM
Pervasive Authentication for IoT: ARC Processors with PUFs
Pim Tuyls, CEO, Intrinsic-ID 

This presentation will explain Physical Unclonable Functions (PUF) technology and how it can be used for authentication and encryption in IoT and embedded systems. Also, it will cover how PUF is integrated into the ARC architecture and how it interacts with other security features and crypto accelerators. The presentation includes an example using PUF to authenticate a sensor to the cloud and guidance for designers who need to find a balance between performance, code size, and gate count.

4:30 PM - 5:00 PM
Embedded Natural Language Voice Interfaces
Kashif Kahn, CEO, Sage Senses 

Advances in machine learning and embedded engineering technologies now make it possible to design and implement sophisticated natural language voice interfaces on ordinary microcontrollers. Embedded voice interfaces address connectivity, bandwidth, latency, energy, and/or privacy issues associated with cloud-based speech systems. They can be utilized either as a complement (eg. backup) or as an alternative to cloud-based speech systems. For most “command-and-control” applications in consumer and industrial domains, a natural language voice interface can be deployed on a microcontroller with less than 1 MB of RAM+ROM and 200 MHz CPU. Further, a developer can train a sophisticated Natural Language Understanding (NLU) engine for his voice interface with a small amount of data.

5:00 PM - 5:30 PM
The Case for Trace
Hugh O’Keeffe, Engineering Director, Ashling 

Embedded debugging techniques have evolved from printf() to the more advanced techniques used today including run-control debug and real-time trace. This presentation will explain these two approaches and discuss the advantages of real-time trace and why it is suitable for validating and debugging complex systems including multicore architectures based on DesignWare ARC Processors. Specific use-cases will be presented showing how to use real-time trace to identify and solve common errors.

Embedded Vision Track

11:00 AM - 12:30 PM
Advanced Vision Capabilities for Next-Generation SoCs
Bo Wu, Embedded Vision Applications Engineer, Synopsys 

The availability of specialized high-performance processors is making it possible to integrate vision capabilities into SoCs, giving them the ability to see and interpret their surroundings. These heterogeneous multicore processors support HD resolutions with low power consumption and include specialized vision engines to improve accuracy. Supporting these processors are a range of tools including OpenVX™, OpenCL™, and OpenCV that greatly improve developmental productivity. This presentation details the architecture of an embedded vision processor family and the open source vision tools used to program and ensure efficient resource utilization of the heterogeneous multicore platform.

12:30 PM - 1:30 PM

1:30 PM - 2:30 PM
Embedded Vision: Where We Are and Where We’re Going
Jeff Bier, Founder, Embedded Vision Alliance and President, BDTI 

Computer vision has rapidly transitioned from a research topic to a mainstream technology with applications in virtually every sector of our economy. But what we are seeing today is just the beginning. This presentation provides an insider's view of the state of embedded vision technology and applications today, and predictions on how the field will evolve in the next few years. It will explore the impact of game-changing technologies such as deep neural networks, and highlight new products and applications that illuminate what we can expect from visually intelligent devices in the near future.

2:30 PM - 3:00 PM
The Vision API Landscape 
Neil Trevett, President, Khronos and Vice President, NVIDIA

The choice of hardware acceleration APIs for parallel computation and vision processing is complex and rapidly evolving. Many of the industry-standard APIs such as OpenCL and OpenVX have been upgraded, while the industry begins to adopt the new generation of low-level, explicit GPU APIs, such as Vulkan, that tightly integrate graphics and compute. Some of these APIs, like OpenVX and OpenCV, are vision-specific, while others, like OpenCL and Vulkan, are general-purpose. Which one(s) should you use for your project? This presentation provides an update of the landscape of APIs for vision software development, explaining where each one fits in the development flow. It also highlights where these APIs overlap and where they complement each other, and previews some of the latest developments.

3:30 PM - 4:15 PM
Using the OpenCL C Kernel Language for Embedded Vision Processors
Seema Mirchandaney, Manager, Software Engineering, Synopsys 

OpenCL C is a programming language that is used to write computation kernels. This presentation will focus on the benefits and ease of programming vision-based kernels using the key features of OpenCL C. The language extensions that allow programmers to take advantage of hardware features typical of embedded vision processors, such as wider vector widths, sophisticated accumulator forms of instructions, and scatter/gather capabilities, will be described. Advanced topics, such as whole function vectorization support available in the compiler and the benefits of hardware support for predication in the context of lane-based control flow and OpenCL C will also be covered.

4:15 PM - 5:00 PM
Visual Perception and Computer Vision for Surveillance and Automotive
Vassilis Tsagaris, CEO, Irida Labs 
Vangelis Vassalos, Sr. Embedded Software Engineer, Irida Labs 

Irida Labs offers an extensive computational photography, vision perception and analytics portfolio of optimized IP cores, applicable to the demanding security, surveillance and automotive markets. Irida Labs has optimized OpenVX-based versions of its video stabilization, low-light video enhancement and de-noise IP cores, ViSTA-EV, EnLight-EV and DeNoise-EV for the DesignWare EV processors, with a motion profile for surveillance and automotive. This presentation will show the profiling results of single-core and multi-core implementations of these cores and will discuss future plans for porting Irida Labs’ face recognition and scene analysis IP cores, using the DesignWare EV processor object detection engine for CNN-based processing.

5:00 PM - 5:30 PM
Targeting CNNs for Embedded Platforms
A.G. Karunakaran, Founder and CEO, MulticoreWare

MulticoreWare designs convolutional neural network (CNN) applications that target embedded platforms and execute within strict compute, memory, and power constraints. This presentation will discuss the challenges encountered in developing CNNs for embedded platforms and some of the techniques used to target modern embedded designs.

5:30 PM – 7:00 PM
Networking Reception 

Wrapping the ARC Processor Summit will be a reception where attendees can enjoy snacks, beverages and network with fellow attendees, our partners, and Synopsys staff. Enter drawings for chances to win great prizes throughout the reception.


Demos will be set up during lunch and at the networking reception, giving you a chance to see a range of compelling solutions to help you meet your design requirements, from embedded vision and sensor fusion applications to debug and security with PUF technology.

ARC Processors in a High-Performance SSD Drive - Starblaze
This demo will show the features and capabilities of the ARC HS processors in SSD applications. This will be shown in the turn-key SSD controller solution from Starblaze.

Booting ARC Linux Quickly with the ARC HS38 VDK - Synopsys
This demo will show an ARC HS38-based system booting Linux on an ARC HS38-based Virtualizer Development Kit.

dotStack™ - An efficient, small footprint, Bluetooth stack for Embedded Devices - Searan
Searan’s highly efficient, ultra-small, Bluetooth stack is Bluetooth SIG compliant and enables new classes of low cost and low power embedded devices. The demonstration will show Searan’s dotStack™ running on the ARC EM Starter Kit development platform featuring both Bluetooth Classic and BLE examples.

Efficiently Implementing Security Functions for Low-Power IoT Edge Devices - Intrinsic-ID
Authentication and the privacy and security of sensitive information has become a concern with the proliferation of connected devices. This demonstration platform, consisting of Intrinsic-ID’s PUF technology operating on Synopsys’ ARC EM Processor, shows secure, authenticated logging of sensor values to a cloud service.

EEMBC BLEmark Benchmark
EEMBC is a non-profit, industry association that was formed in 1997 to develop performance benchmarks for the hardware and software used in embedded systems. EEMBC benchmarks help predict the performance and energy consumption of embedded processors and systems in a range of applications (autonomous driving, mobile imaging, Internet of Things, scale-out servers, and mobile devices) and disciplines (processor core functionality, floating-point, multicore, and energy consumption). This exhibit will highlight the EEMBC BLEmark benchmark, measuring the efficiency of an IoT edge-node device transmitting over a Bluetooth connection; this will help users predict the battery life of their IoT device.

The Evolution of IoT - Demonstration Platform for "Always-on" Functions - Synopsys
Voice recognition, face detection and 9D motion sensor fusion are some of the key functions in the new “always-on” paradigm for IoT devices. This silicon-based demonstration platform showcases these functions, leveraging Synopsys’ DesignWare Smart Data Fusion IP Subsystem and Renesas’ MONOS flash technology for efficient sensor processing combined with high-performance analysis.

Optimized Debug Solutions for DesignWare ARC Processors - Ashling Microsystems
Ashling provides embedded developers with high quality debug solutions including JTAG Debug Probes and High Capacity Trace Probes for all DesignWare ARC Processors. Ashling’s OPELLA-XD is a high-speed cJTAG/JTAG debug probe and the ULTRA-XD is a high-performance real-time trace (RTT) probe for embedded software development. Ashling will show the integration of the OPELLA-XD and ULTRA-XD debug solutions with the ARC MetaWare and GNU toolchains for ARC Processors.

PLS10 Sub-threshold Implementation of ARC EM5D Processor-based Smart Data Fusion IP Subsystem - PLSense
The PLSense PLS10 chip integrates the DesignWare Smart Data Fusion IP Subsystem with ARC EM5D processor and is capable of working from the sub-threshold domain of 0.45V up to the standard voltage of 1.1V.  The demo will show different functions, including CoreMark and Dhrystone 2.1, running on the PLS10 at different speeds and operating voltages and achieving the best power per operation, which is up to 7x better from other competitive solutions.

Real-Time Object Detection Using HAPS Physical Prototyping - Synopsys
This demo showcases the HAPS® integrated physical prototyping solution running a DesignWare EV5x vision processor for detecting speed signs. The HAPS system is processing real-time input from the EV5x processor and displaying each speed sign detected.

SAFERTOS - An RTOS for Safety-Critical Software - Wittenstein High Integrity Systems
SAFERTOS is a safety certified Real Time Operating System (RTOS) for embedded processors. It delivers high performance and pre-certified dependability, whilst utilizing minimal resources. The demonstration will show several example applications running SAFERTOS on the ARC EM Starter Kit.

Universal Debug Solutions for Embedded Systems - Lauterbach
Lauterbach is the largest producer of hardware assisted debug tools. Its TRACE32 product is a state of the art debugger with the universal user interface, PowerView, that runs on the user’s workstation and the smart debug probe, PowerDebug, which connects to the target via USB or Ethernet. Lauterbach supports all DesignWare ARC Processors, including support for multi-core, SmaRT trace and ARC Real-Time Trace (RTT). Lauterbach will demonstrate the use of these tools for ARC Processors.

Zephyr Project – An Open Source RTOS for Secure IoT - Zephyr Project (Linux Foundation)
The Zephyr Project is a small, scalable real-time operating system for use on resource-constrained systems, including ARC EM Processors. As a true open source project, the community can evolve the Zephyr Project to support new hardware, developer tools, sensor and device drivers. The demonstration will show a sensor fusion application running on the Zephyr RTOS ported to the ARC EM Starter Kit. A Zephyr Project representative will also be available to answer questions on Zephyr and how to become part of the project.

Synopsys will provide complimentary parking and WiFi for event attendees.