Javier De La Cruz, fellow and senior director of system integration at Arm, expressed similar sentiments. According to Cruz, multi-die systems create new variations of traditional design issues such as thermal limitations that require cross-industry collaboration and partnership. Cruz also pointed out that while thermal behavior may be somewhat easier for AI-driven EDA to analyze on multi-die systems with 2.5D packaging, 3D stacking introduces additional temperature variations that can be challenging to simulate and model.
Henry Sheng, Synopsys R&D group director, noted that engineers can overcome various multi-die systems design challenges like thermal issues with new EDA tools, additional standards, and wider cooperation across the semiconductor world. According to Sheng, multi-die systems share a host of interdependencies that designers can’t efficiently or cost-effectively resolve in isolation. That’s why multi-die systems require a holistic approach spanning EDA, IP, foundries, and OSATs.
Sheng highlighted the UCIe specification as an example of industry collaboration that can help further accelerate the adoption of multi-die systems. Introduced in March 2022, UCIe standardizes multi-die systems by streamlining interoperability between dies on different process technologies from various suppliers. The specification currently supports 2D, 2.5D, and bridge packages, with 3D packaging support expected in future iterations. UCIe, which supports up to 32 Gbps of bandwidth per pin, is the only standard with a complete stack for die-to-die interfaces.