This research was, in part, funded by the U.S. Government. The views and conclusions contained in this document are those of the authors and should not be interpreted as representing the official policies, either expressed or implied, of the U.S. Government.
Over the years, we’ve had the pleasure of collaborating with numerous defense contractors, silicon foundries and universities to develop cutting-edge chipset design, verification and IP technologies.
Recently we add to that legacy, with the announcement that the Defense Advanced Research Projects Agency (DARPA) has selected Synopsys as a Prime Contractor for the Automatic Implementation of Secure Silicon (AISS) program.
Over the next four years, we have been tasked with bringing security to the forefront of the chipset design process that has been previously hyper-focused on performance and cost objectives. Not only that, but the final “security-aware” EDA tools developed are expected to accelerate the time-to-market timeline from architecture to security-hardened product from one year to one week.
In addition to this shorter timeline, the level of design automation included in this project’s scope is unusual in the best sense of the word.
While traditional integrated circuit designs (and related IC workflow) are usually focused on delivering functional performance objectives at a reasonable cost, they don’t often start from a foundation of security.
That foundation of security begins early in the hardware development process, well below the software layer. Synopsys DesignWare® Security IP, integrated in the expected DARPA system on a chip (SoC), will provide the ‘root of trust’ tuned for the target application, enabling chip manufacturers and their OEM/ODM customers to create a strong cryptographic device identity that is permanently bound to that unique device instance.
Through the AISS program, Synopsys will be on the ground floor of creating secure silicon architecture for a huge variety of applications. The end product could allow non-expert designers to engage in silicon engineering that is automatically optimized to achieve performance goals in power, area, speed and security.