VCS Native Low Power (NLP)

VCS Native Low Power (NLP)

Accurate, Comprehensive Low Power Simulation

Adoption of low power design techniques is growing rapidly to enable ASICs and SoCs to support the advanced power management required across today's electronic products, from mobile devices to servers and networking. Advanced low power techniques such as Power Gating, Retention, Low-VDD Standby, and Dynamic Voltage Scaling (DVS) employ voltage control to enable fine-grained power management. Designs are partitioned into power domains that can be separately controlled by one or more of these low power design techniques. Increasingly stringent power requirements have necessitated the use of multiple supply voltages. Low power designs typically operate in different modes, with each mode corresponding to one or more power states. Comprehensive verification of low power designs requires verification not just in all the power states, but also of the specified transitions and transition sequencing between power states as the design moves from one operating mode to another. A single bug in any of these incredibly complex scenarios may cause functional failures in silicon.

Simulation Challenges for Low Power Designs

It is no longer sufficient to simulate a design assuming voltage to be a constant. Most designs today have voltage changes during operation, such as when a design enters a low Vdd standby state or utilizes DVS modes. This requires simulation to understand voltage levels to accurately resolve signal values and timing. Power state transitions require understanding of the dynamic nature of voltage and its effect on logic; outputs become a function of not only the logical value on the inputs, but also the voltage levels of those values. Traditional ("always-on") simulations will produce inaccurate and misleading results, potentially allowing bugs to escape and manifest in silicon.

In addition, multi-voltage designs have design components operating under different supply voltages from multiple supply rails. Traditional simulators don't have the intelligence to understand the relationship between different supply voltages and what they drive, causing potential silicon failures that go undetected in simulation.

Power-on resets for low power designs involve turning power domains on in a strictly-defined sequence, where a powered-up domain may subsequently help power up the next domain. Understanding the voltage transitions and dependencies during power-on reset is essential to accurately and completely verify a low power design.

VCS with Native Low Power ("NLP") Mode

VCS® NLP natively performs power aware simulation with a complete understanding of the UPF-defined power network, at RTL prior to implementation. This uniquely allows engineers to comprehensively verify correct behavior of designs that use advanced voltage control techniques for power management and catch potentially expensive low power bugs very early in the design process

Key Features and Benefits

  • Catch LP bugs early and quickly with accurate simulation of designs using advanced low power techniques, including Power Gating and Retention
  • Voltage-level aware simulation accurately verifies designs with Low-VDD Standby and DVS
  • Infrastructure to model and correctly simulate Multi-Rail macros leads to increased bug detection for multi-voltage designs
  • Built-in, automated assertions derived from analysis of the design and power intent mitigate the risk of undetected bugs and increase verification productivity
  • Automated coverage tracking and reporting helps track overall verification coverage
  • Production-proven support for industry-standard IEEE 1801-2009 Unified Power Format (UPF)

VCS Native Low Power Flow

VCS NLP takes in the same Verilog or VHDL RTL or gate-level netlist representation of the design as in standard flows and accepts the same testbench as in standard flows (optionally augmented for low power checks). However, the native low power flow requires power intent to be specified in a UPF format file, which is loaded into VCS with the design and the testbench. VCS NLP reads this UPF, models the entire power network described in the UPF, and accurately understands the low power policies and voltage events. VCS NLP produces a log file and an error and warnings report for all violations related to multi-voltage checks. 

VCS Native Low Power Flow chart