It is no longer sufficient to simulate a design assuming voltage to be a constant. Most designs today have voltage changes during operation, such as when a design enters a low Vdd standby state or utilizes DVS modes. This requires simulation to understand voltage levels to accurately resolve signal values and timing. Power state transitions require understanding of the dynamic nature of voltage and its effect on logic; outputs become a function of not only the logical value on the inputs, but also the voltage levels of those values. Traditional ("always-on") simulations will produce inaccurate and misleading results, potentially allowing bugs to escape and manifest in silicon.
In addition, multi-voltage designs have design components operating under different supply voltages from multiple supply rails. Traditional simulators don't have the intelligence to understand the relationship between different supply voltages and what they drive, causing potential silicon failures that go undetected in simulation.
Power-on resets for low power designs involve turning power domains on in a strictly-defined sequence, where a powered-up domain may subsequently help power up the next domain. Understanding the voltage transitions and dependencies during power-on reset is essential to accurately and completely verify a low power design.