Accurate, Comprehensive Low Power Simulation
Adoption of low power design techniques is growing rapidly to enable ASICs and SoCs to support the advanced power management required across today's electronic products, from mobile devices to servers and networking. Advanced low power techniques such as Power Gating, Retention, Low-Vdd Standby, and Dynamic Voltage Scaling (DVS) employ voltage control to enable fine-grained power management. Designs are partitioned into power domains that can be separately controlled by one or more of these low power design techniques. Increasingly stringent power requirements have necessitated the use of multiple supply voltages. Low power designs typically operate in different modes, with each mode corresponding to one or more power states. Comprehensive verification of low power designs requires verification not just in all the power states, but also of the specified transitions and transition sequencing between power states as the design moves from one operating mode to another. A single bug in any of these incredibly complex scenarios may cause functional failures in silicon.