From high end servers to consumer electronics to wearables, devices are designed to operate within a specific power envelope. SoC teams utilize varying levels of sophisticated low-power design techniques to achieve power targets, and require accurate power analysis to validate that these power targets are indeed met. However, accurate power analysis happens too late in the traditional design flow to allow for design changes if power targets are missed. Consequently, designs are either taped out on time without meeting power specifications, or schedule delays are incurred to ensure power targets are met. Both situations are undesirable and can incur significant costs, not to mention missed time-to-market windows. Hence, there is a pressing need for power analysis that is accurate enough to base design changes on, yet early enough in the flow to accommodate design changes.