DVCon U.S. 2019

Visit Synopsys at Booth #101

Location: DoubleTree Hotel, 2050 Gateway Place, San Jose, California

Exhibit Times:

Monday, February 25, 5:00pm - 7:00pm

Tuesday, February 26, 2:30pm - 6:00pm

Wednesday, February 27, 2:30pm - 6:00pm

Industry Leaders Verify with Synopsys

At this luncheon, you will hear industry experts share their viewpoints on what is driving SoC complexity, how their teams have achieved success, how you can apply their insights on your next project as well as discussions about the latest developments in the verification landscape and advanced technology.

Additional Synopsys Sessions

Tuesday, February 27, 10:30am - 12:00pm | Gateway Foyer

Overcoming Low Power Verification Challenges for Mixed ASIC and FPGA SoCs

Tuesday, February 27, 10:30am - 12:00pm | Gateway Foyer

Using UPF Information Model to Write Re-usable Low Power Testbenches and Customized Coverage Models for Low Power

Tuesday, February 27, 10:30am - 12:00pm | Gateway Foyer

Timing Coverages: An Approach to Analyze Performance Holes

Tuesday, February 27, 3:00pm - 4:30pm | Fir

Simulation Runtime Optimization of Constrained Random Verification using Machine Learning Algorithms

Wednesday, February 28, 3:00pm - 4:30pm | Oak

UVM and UPF: An Application of UPF Information Model

Wednesday, February 28, 3:00pm - 4:30pm | Fir

Connectivity and Beyond