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DVCon U.S. 2019
Location: DoubleTree Hotel, 2050 Gateway Place, San Jose, California
Exhibit Times:
Monday, February 25, 5:00pm - 7:00pm
Tuesday, February 26, 2:30pm - 6:00pm
Wednesday, February 27, 2:30pm - 6:00pm
Synopsys Luncheon
Industry Leaders Verify with Synopsys
At this luncheon, you will hear industry experts share their viewpoints on what is driving SoC complexity, how their teams have achieved success, how you can apply their insights on your next project as well as discussions about the latest developments in the verification landscape and advanced technology.
Tutorial
Tackling the Complexity Problem in Control and Datapath Designs with Formal Verification
Thurs, February 28, 8:30 am - 11:30am | Fir
Learn More
Workshop
Using Simulation Acceleration to Speed Block and Platform Level IP Verification
Thurs, February 28, 1:00pm - 2:30pm | Fir
Learn MoreAdditional Synopsys Sessions
Tuesday, February 27, 10:30am - 12:00pm | Gateway Foyer
Overcoming Low Power Verification Challenges for Mixed ASIC and FPGA SoCs
Tuesday, February 27, 10:30am - 12:00pm | Gateway Foyer
Tuesday, February 27, 10:30am - 12:00pm | Gateway Foyer
Timing Coverages: An Approach to Analyze Performance Holes
Tuesday, February 27, 3:00pm - 4:30pm | Fir
Simulation Runtime Optimization of Constrained Random Verification using Machine Learning Algorithms
Wednesday, February 28, 3:00pm - 4:30pm | Oak
UVM and UPF: An Application of UPF Information Model
Wednesday, February 28, 3:00pm - 4:30pm | Fir