Cloud native EDA tools & pre-optimized hardware platforms
Design Technology Co-Optimization (DTCO) is a methodology that helps semiconductor fabs reduce cost and time-to-market in advanced process development. The Synopsys DTCO Solution enables the efficient evaluation and down-selection of new transistor architectures, materials and other process options using power, performance and area (PPA) design metrics.
By deploying DTCO, technology development teams develop new patterning techniques with Proteus Mask Synthesis and Sentaurus Lithography, model new materials with QuantumATK, evaluate and optimize new transistor architectures with Sentaurus TCAD and Process Explorer and extract compact models with Mystic. Design rules derived from these process options are then used to design and characterize a standard cell library with SiliconSmart and HSPICE, and to carry out block-level PPA evaluations using the Synopsys Fusion Technology physical implementation flow based on IC Compiler II, StarRC, PrimeTime and IC Validator.
Synopsys DTCO Flow