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DC Explorer
Early RTL Exploration Accelerates Design Schedules
DC Explorer enables early RTL exploration leading to a better starting point for RTL synthesis and accelerating design implementation. With tolerance to incomplete design data, 5-10X faster runtimes and 10% timing and area correlation to DC Ultra (Topographical), it provides early visibility into implementation results. DC Explorer enables designers to efficiently perform what-if analyses of various design configurations early in the design cycle to speed the development of high quality RTL and constraints and drive a faster, more convergent design flow. It also generates an early netlist that can be used to begin physical exploration in IC Compiler. With push-button access to IC Compiler design planning from inside the RTL exploration environment, DC Explorer lets designers easily create and modify floor plans very early in the design cycle.
DC Explorer accelerates development of high quality RTL and constraints leading to a faster, more convergent design flow
Benefits
- Early RTL exploration creates a better starting point for RTL synthesis
- Tolerance of incomplete design data for faster development of high quality RTL and constraints
- Pre and post-synthesis routing congestion analysis and reporting for early RTL feedback
- Histogram showing levels of logic for RTL analysis and potential timing improvement
- Cross-probing between RTL, schematic, timing reports, congestion and physical views for fast debug
- 5-10X faster runtime than RTL synthesis for efficient what if analyses
- 10% timing and area correlation with DC Ultra (Topographical) for early visibility into implementation results
- Optionally reads in physical constraints for tighter correlation with DC Ultra (Topographical)
- Push-button access to IC Compiler design planning for faster floor plan development and exploration
- Script-compatible with DC Ultra for easy deployment into existing flows
- Support for UPF for early power intent development
- Multicore compute platform support delivers additional 2X runtime speedup on 4 cores