Achieving Design Robustness in Signoff for Advanced Node Digital Designs

SemiWiki Webinar

As designs migrate to cutting edge single digit nanometer technologies, designing high yielding products that quickly enter the market is key to remain competitive in the chip industry. Advanced node digital designers are looking for ways to improve design robustness without sacrificing their project schedules. As design sizes continue to grow and physical designers continue to employ hierarchical methodologies, new design techniques must be used to complement traditional corner analysis for handling process variation and to accurately sign-off a hierarchical physical design from an implementation and analysis point of view. This webinar talks about some of the new techniques available from EDA tools such as StarRC to tackle these advanced node hierarchical physical design challenges from an interconnect perspective.