Fast and Accurate Functional ECOs with Synopsys Formality ECO

Synopsys Webinar | On-Demand

To achieve maximal quality of results (QoR) in synthesis, it requires leveraging retiming, multibit banking, and advanced datapath optimizations, which are part of the Synopsys Fusion Compiler™ implementation solution. However, during the late-stage functional ECO (engineering change order) phase, the automated ECO tool needs to be sophisticated enough to generate optimal patches in the presence of such aggressive optimizations. Given these ECO implementations occur at a late stage, they always need to be implemented rapidly while ensuring that the functionality and timing requirements are met without any sacrifice to the synthesis QoR. 

The Synopsys Formality® ECO solution can start up front at the ECO RTL and understand the optimizations that Synopsys Fusion Compiler employs, thus enabling rapid creation of ECOs. 

In this Synopsys webinar, Intel shares its experience using Synopsys Formality ECO, an efficient, automated solution for implementing functional ECOs fast, accurately, and predictably. The presentation will detail how Synopsys Formality ECO helped with optimal patch generation which enabled Intel to meet its time-to-market requirements.

Speakers

Listed below are the industry leaders scheduled to speak.

Sai Kumar Yella

Applications Engineer, Staff
Synopsys

Sai Kumar Yella is a Staff Applications Engineer at Synopsys. He has over 10 years of experience in Synopsys front-end tools spanning Synopsys Design Compiler, Synopsys Formality, and Synopsys Fusion Compiler. Sai Kumar holds a bachelor’s degree in Electronics and Communications engineering from JNTU (BVRIT).

Sorana Lazarovici

Senior Hardware/CAD Engineer
Intel Corporation, CCD

Sorana Lazarovici is a Senior Hardware/CAD Engineer at Intel Corporation, CCD. She has over 25 years of experience in front-end activities like logic design and simulation, including clusters leading (like MAC or PCIe) and back-end different activities including synthesis, static timing analysis and formal verification, using Cadence Conformal-LEC and Synopsys Formality. Sorana holds an MBA degree from Hebrew University and a B.Sc. degree in Computer Engineering from Technion Institute.

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