Cloud native EDA tools & pre-optimized hardware platforms
3DIC Design from Concept to Silicon
For some high-performance computing (HPC) designs, monolithic SoCs aren’t producing the scalability and yield that designers are looking for. New trends towards 3DIC design are emerging introducing new design challenges, such as reliable die-to-die connectivity, high bandwidth memory, integration, and 2.5D or 3D packaging options. This webinar will outline the different market trends for 3DIC designs and explain how designers can maintain such new trends to deliver their designs with optimized latency, power, performance, and area. We will also demonstrate the construction of a 3DIC design and our 3rd generation HBM interposer auto-routing solution.
Attend this Synopsys webinar to:
Listed below are the industry leaders scheduled to speak.
Senior Staff Applications Engineer
Jennifer Pyon is a product engineer in 3DIC Compiler at Synopsys. She has over 25 years of industry experience in VLSI design and EDA development in digital design, physical optimization & static timing analysis. She developed and deployed key technologies for advanced technology node design such as variation-aware timing analysis, timing closure with ECO, hierarchical design, delay calculation in advanced technology node, until recently involved in 3DIC construction and auto HBM routing. Jennifer has a BS degree in Electrical Engineering from Ajou university, South Korea.
Staff Applications Engineer
Eric Means is an Applications Engineer in Hillsboro, Oregon supporting Synopsys 3DIC Compiler users. He has worked with ASIC and EDA customers for 25 years at NEC, Renesas, & Synopsys. He has a BS in Electrical Engineering from Washington State University and an MS in Computer Engineering from the Oregon Graduate Institute.
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