RTL engineering change order (ECO) is vital to ensuring proper functionality of integrated circuits (ICs). Retiming and auto ungrouping optimize RTL implementation and enhance PPA. However, aggressive optimizations in CPU RTL designs present challenges due to increased design complexity and potential mapping issues.
Synopsys Formality ECO offers an efficient and accurate solution for RTL ECO by automating the comprehensive ECO flow, analysing differences between original RTL and ECO RTL, generating patches, and validating changes. Formality ECO also supports aggressive RTL optimization techniques, including retiming and auto ungrouping, while providing advanced analysis and debug features to streamline the ECO process.
In this Synopsys webinar, presenters from SiFive will share the advantages of Synopsys Formality ECO on their overall ECO cycle which has enhanced patching capabilities and resulted in faster verification runtime leading to improved TAT. With the retimed and flattened design, it is difficult to generate the sizable patch for fast CPUs designs targeted by SiFive. SiFive designs have strict requirements on the patch size, patch affecting hierarchies, changes applicable to RTL and ease of implementation at route_opt stage. By using Synopsys Formality ECO suite, SiFive has been able to generate a hassle-free patch and verify it 3-5x faster than traditional formal verification ensuring performance of the CPU.