Cloud native EDA tools & pre-optimized hardware platforms
Long sitting in the wings, 3DICs are finally coming of age and aggressively making their way into the mainstream – bringing with them massive opportunities to shape a new "scaled-up," data-driven, and processing-centric economy. By providing unfettered performance scaling in physically constrained footprints or allowing a heterogeneous mix-and-match approach to maximizing target-application-optimized process technologies, 3DIC offers vast potential.
In this panel session, industry luminaries from AMD, Intel, Qualcomm, Stanford University and Synopsys will discuss emerging usage of 3DIC across multiple verticals, including HPC, datacenter and mobile. They will share insights on its abundant promise, challenges, and how to move this exciting technology faster and further into the design ecosystem and normalize it as a go-to methodology.
Dr. Raja Swaminathan is a Senior Fellow at AMD responsible for package architectures and advanced technology strategy and development with ecosystem partners. He was a package architect at Intel for 13 years, moved to Apple to develop their M1x silicon package architectures before moving to AMD to drive their industry leading chiplet architecture integration, including the recently released 3D VCache and 2.5D EFB package architectures.
Dr. Raja received his Bachelors’ from IIT Madras and PhD from Carnegie Mellon University. He has over 35 US patents in the field; he is an IEEE Senior Member and is on the technical advisory board for the Semiconductor Research Corporation (SRC).
Sr. Principal Engineer
Pushkar Ranade is a Senior Principal Engineer in the Accelerated Computing Systems and Graphics group at Intel Corporation. He works on process technology definition and design-technology co-optimization. Pushkar’s work has spanned Intel’s silicon design organizations and technology development organizations.
Pushkar first joined Intel in 2003 as member of the Logic Technology Development (LTD) group in Oregon, where he contributed to transistor process integration of 65nm, 45nm and 22nm nodes from early pathfinding through volume ramp.
Pushkar holds a PhD in Engineering from University of California at Berkeley.
Sr. Dir. Engineering
Mamta Bansal is Sr. Director of Engineering at Qualcomm Technologies, Inc., leading the Global CAD Digital Implementation. She has over 25 years of experience in the semiconductor industry.
Mamta joined Qualcomm in 2010 and has led worldwide engineering teams responsible for RTL2GDS design flow for Qualcomm SoCs in cutting-edge advanced process nodes.
ACM/IEEE Fellow EE & CS
Subhasish Mitra is Professor of Electrical Engineering and of Computer Science at Stanford University. He directs the Stanford Robust Systems Group, leads the Computation Focus Area of the Stanford SystemX Alliance, and is a member of the Wu Tsai Neurosciences Institute. His research ranges across Robust Computing, NanoSystems, Electronic Design Automation (EDA), and Neurosciences. Professor Mitra also has consulted for major technology companies including Cisco, Google, Intel, Samsung, and Xilinx.
Professor Mitra's honors include various awards, including the Harry H. Goode Memorial Award (by the IEEE Computer Society for outstanding contributions in the information processing field), Newton Technical Impact Award in EDA (test-of-time honor by ACM SIGDA and IEEE CEDA), the University Researcher Award, the Intel Achievement Award (Intel’s highest honor), and the US Presidential Early Career Award.
Professor Mitra is an ACM Fellow and an IEEE Fellow.