HPC has traditionally been associated with supercomputers of which the 2nd fastest in the world resides at the Lawrence Livermore National Laboratory, about an hour from Silicon Valley. With an estimated 1,572,480 processing cores, this machine called “Sierra,” can perform almost 100 Petaflops per second. You need a computer that powerful if you are trying to solve some really hard problems like simulating nuclear decay and potential instability issues of our aging nuclear weapons arsenal. Less scary but seemingly just as difficult tasks involve weather prediction, DNA sequencing, and molecular modeling. Solving these problems does come at a pretty big power cost: 7.4 Megawatts to be exact, or the equivalent of powering 7,000 to 8,000 homes.
Today, HPC is not just for solving the unsolvable problems of the world. It’s now being used for non-research applications. For rendering the latest CGI effects in movies and shows like Star Trek: Discovery or Star Wars: Rise of Skywalker. It can be used to teach your car to drive by itself, to unlock your phone by recognizing your face, or help your virtual assistant recognize when you are talking to it and answer your questions.
With a lot of these applications, the latency of communicating with a remote compute farm puts an emphasis on localized processing which means putting HPC in your phone, your virtual assistant, your laptop, or your car.
When you think about the idea of putting a scaled-down Sierra supercomputer on a chip, you start to imagine how HPC can solve your everyday problems. However, scaling that many processing elements on a single chip pose multiple design challenges. First and foremost is power consumption. For any HPC application, you need the lowest power possible because megawatts are costly, even for a government lab, and even if you reduced power by several orders of magnitude, your device would probably burst into flames. Second, the amount of communication between processing elements requires higher placement densities to shorten interconnect and delay latency. And third, HPC processing hardware is pushing clock frequencies beyond 3GHz which requires the latest process technologies and tools to handle new fabrication rules for mask design, lithography, and fabrication.