Synplify Pro

Logic Synthesis for FPGA Design

Synplify Pro® FPGA synthesis software is the industry standard for producing high-performance and cost-effective FPGA designs. Synplify software supports the latest VHDL and Verilog language constructs including SystemVerilog and VHDL-2008. The software also supports FPGA architectures from a variety of FPGA vendors, including Altera, Achronix, Lattice, Microsemi and Xilinx, all from a single RTL and constraint source. Synplify Pro software uses a single, easy-to-use interface and has the ability to perform incremental synthesis and intuitive HDL code analysis.

For designers of large designs that need the fastest possible synthesis runtimes and the highest quality timing, area and power results. Synplify® Premier software provides all of the features of Synplify Pro as well as a comprehensive suite of tools for advanced FPGA design, see the Synplify Feature Comparison Chart.

Logic Synthesis for FPGA implementation

Synplify Pro logic synthesis includes:

  • Incremental, block-based and bottom-up flows for consistent results from one run to the next
  • Automatic compile points incremental flow for up to 4x faster runtime while maintaining QoR
  • Accelerated runtimes with support for up to 4 processors
  • Scripting and Tcl/Find support for flow automation and customizable synthesis, debug and reporting
  • Optimal area and timing results using FPGAs from Achronix, Altera, Lattice, Microsemi, Xilinx
  • Hierarchical team design flow allowing parallel and/or geographically distributed design development
  • Comprehensive language support including Verilog, VHDL, SystemVerilog, VHDL-2008 and mixed-language design
  • FSM Compiler and FSM Explorer for automatic extraction and optimization of finite state machines from RTL
  • Graphical state machine viewer to automatically create bubble diagrams for debugging and documenting FSMs
  • Automatic memory and DSP inference provides automatic implementation of a design with optimal area, power and timing quality of results
  • Incremental static timing for analysis allows updates to timing exception constraints with immediate visibility into results, without re-synthesis
  • HDL Analyst interactive graphical analysis and debug tool for design diagnosis, problem isolation and functional and performance analysis