Identify RTL Debugger

Simulator-like Visibility into FPGA Hardware Operation

The Identify® RTL debugger allows you to instrument RTL HDL and then, still at the RT-Level, debug the implemented FPGA on live, running hardware. The Identify FPGA debug software verifies a design in hardware, similar to simulation – only much faster and with in-system stimuli.

The Identify RTL debugger allows you to designate sample triggers, navigate the design graphically, and mark signals in the RTL that are to serve as probes. After synthesis, the results are viewed and annotated onto the RTL source code, the HDL Analyst® RTL View, or third party, waveform viewer. This ensures RTL-to-implementation equivalence and correct operation of the FPGA design.

Features

  • Support for Altera, Microsemi and Xilinx devices
  • Ability to instrument and debug an advanced FPGA design directly from RTL source code
  • Advanced trigger creation allows the viewing of desired design operation scenarios and probe specific nodes in the circuit
  • Visibility into the internal design while operating at full speed
  • Display of debug results superimposed on top of RTL source, RTL structural view, or with a waveform viewer
  • Selectively view up to 8 distinct groups of internal nodes with a single Identify IICE during a debug session
  • Synthesis and placement bypass option allows rapid instrumentation changes of Virtex-7/6/5 FPGA
  • Compatible with Synopsys verification solutions Verdi3™ and Siloti for automated debug and visibility of FPGA-based prototypes
Identify RTL debugger session with source code annotation of sample data

Identify Debugger session with source code annotation of sample data
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