Large Language Model - the "Current Big Thing" in the Semiconductor World

Session Chair: Sabya Das

Type: Research Special Session

Time: 10:30am - 12:00pm PDT

Location: 3010, Level 3

Next Generation UCIe: Enabling a Thriving Open Chiplet Ecosystem

Organizer: Sashi Obilisetty

Presenter: Yervant Zorian

Type: Engineering Special Session

Time: 10:30am - 12:00pm PDT

Location: 2012, Level 2

Generative Model Based Standard Cell Timing Library Characterization

Presenters: Benson Tsao, Vinson Wu, Wei-Kai Shih

Type: Research Manuscript

Time: 11:00am - 11:15am PDT

Location: 3004, Level 3

Enabling Multi-Die 3DIC Designs with AI-Powered Ecosystem Collaboration

Moderator: Tanuja Rao

Type: Engineering Special Session

Time: 1:30pm - 3:00pm PDT

Location: 2008, Level 2

From Pixels to Chips: AI-Enhanced Layout & Mask Design

Session Chair: Luigi Capodieci

Type: Research Manuscript

Time: 1:30pm - 3:00pm PDT

Location: 3004, Level 3

Performance vs. Sustainability: The Challenge of Energy-Efficient Computing

Organizer: Sabya Das

Type: Research Panel

Time: 1:30pm - 3:00pm PDT

Location: 3012, Level 3

AI-aided Flow for Digital Verification of a Multiprotocol SerDes PHY

Presenters: Celso Figueiredo, Domingos Terra

Type: Engineering Presentation

Time: 2:45pm - 3:00pm PDT

Location: 2010, Level 2

Cooley's DAC Troublemaker Panel

Panelist: Ravi Subramanian

Type: Panel

Time: 3:00pm - 4:00pm PDT

Location: DAC Pavilion, Level 2 Exhibit Hall

Back-end and System Considerations for Chiplets

Session Chair: Frank Schirrmeister

Type: Engineering Presentation

Time: 3:30pm - 5:00pm PDT

Location: 2008, Level 2

SLM Is the New DFT – Are You Ready?

Presenter: Steve Pateras

Type: Engineering Special Session

Time: 3:30pm - 5:00pm PDT

Location: 2012, Level 2

Silicon Startup Forum at DAC - Funding Strategies for Semiconductor Startups

Moderator: Dave Rinehart

Type: Panel

Time: 4:00pm - 6:00pm PDT

Location: 2011, Level 2

Robust Hard Macro Timing Validation: Early Detection of Issues and Automated Feedback for Integration

Presenters: Vaibhav Garg, Mohita Batra, Arjun Saha, Rishabh Srivastava

Type: Engineering Presentation

Time: 4:30pm - 4:45pm PDT

Location: 2010, Level 2

Automated IR Convergence with PrimeClosure IR-ECO

Presenter: Srinivasulu M

Type: Engineering Poster

Time: 5:00pm - 6:00pm PDT

Location: Level 2 Exhibit Hall

Automated IR-ECO Flow: Reducing PDN Violations upto 40-50% and Saving Weeks of Engineering Effort

Presenter: Len Hsu

Type: Engineering Poster

Time: 5:00pm - 6:00pm PDT

Location: Level 2 Exhibit Hall

Leveraging Machine Learning to Automate Waiver Generation for Static Lint Violations

Presenters: Mohan Mangal, Himanshu Kathuria, Jaskaran Ajimal

Type: Engineering Poster

Time: 5:00pm - 6:00pm PDT

Location: Level 2 Exhibit Hall

Methodology to Generate Synthesis Signoff Quality Optimized Registers at RTL and Application of Generated Optimized Registers into RTL and Implementation Design Flows to Improve Productivity

Presenters: Suresh Barla, Bhavana Mallikarjunaiah, Himanshu Kathuria, Jaskaran Ajimal

Type: Engineering Poster

Time: 5:00pm - 6:00pm PDT

Location: Level 2 Exhibit Hall

Boolean Reasoning Guided Ungrouping

Presenters: Eleonora Testa, Giulia Meuli, Elena Teica, Alan Vaz, Vishal Aralikatti, Abhishek Kumar, Brian Lockyear, Luca Amaru

Type: Work-in-Progress Poster

Time: 6:00pm - 7:00pm PDT

Location: Level 2 Lobby

Late Breaking Results: Warpage-Aware Generative Floorplanning for Reliable Advanced Packaging

Presenter: Tung-Chieh Chen

Type: Late Breaking Results

Time: 6:00pm - 7:00pm PDT

Location: Level 2 Lobby

UPF Guided Design Editing for Early Low Power Verification Sign Off

Presenters: Ankit Narang, Sachin Bansal, Vishal Keswani, M.Vaishnavi Reddy, Amit Goldie, Manish Goel

Type: Engineering Presentation

Time: 10:45am - 11:00am PDT

Location: 2010, Level 2

Secondary-Power-Cell-Aware Detailed Placement in Multiple Power Domain Designs

Presenters: Kai-Chuan Yang, Min-Ching Lin

Type: Research Manuscript

Time: 11:45am - 12:00pm PDT

Location: 3004, Level 3

Accellera-Sponsored Luncheon: Can AI Cut Costs in Electronic Design & Verification While Accelerating Time-To-Market?

Panelist: Badri Gopalan

Type: Ancillary Meeting

Time: 12:00 pm - 1:30 pm PDT

Location: 2006, Level 2

Accelerating Tapeout by Months with Cost-Effective Per-Minute EDA Cloud Licensing

Presenters: Vikram Bhatia

Type: Exhibitor Forum

Time: 3:30 pm - 4:00 pm PDT

Location: Level 1 Exhibit Hall

Follow the Logic: Advances in Logic Synthesis

Session Chair: Eleonora Testa

Type: Research Manuscript

Time: 3:30pm - 5:00pm PDT

Location: 3006, Level 3

Revolutionizing Digital ASIC Design through AI

Presenters: Paulo Magno, Ricardo Araujo, Miguel Caetano, Mara Carvalho, Luis Cruz, Luis Francisco

Type: Engineering Presentation

Time: 4:00pm - 4:15pm PDT

Location: 2010, Level 2

A Leap Forward in Formal Verification Using Generative AI

Presenters: Sean Safarpour, Alex Chang

Type: Engineering Presentation

Time: 4:15pm - 4:30pm PDT

Location: 2010, Level 2

Detection of Functional and Current Related Bugs in SoC through Full Chip SPICE Simulations (FCS)

Presenter: Rakesh Shenoy

Type: Engineering Poster

Time: 5:00pm - 6:00pm PDT

Location: Level 2 Exhibit Hall

InsightAlign: A Transferable Physical Design Recipe Recommender Based on Design Insights

Presenters: Sudipto Kundu, Wei Zeng, Wei-Ting Chan, Deyuan Guo

Type: Research Manuscript

Time: 11:15am - 11:30am PDT

Location: 3000, Level 3

Accelerating Design-technology Co-development using Neural Compact Modeling and Data-driven SPICE Simulation​

Presenters: Zhaojie Li, Dehuang Wu, Joddy Wang

Type: Research Manuscript

Time: 11:45am - 12:00pm PDT

Location: 3000, Level 3

A Solution for Intermittently and Fastly Power On Repair​

Presenters: Zhuo Wang, Jian Yu, Fengfeng Tang

Type: Engineering Poster

Time: 12:15pm - 1:15pm PDT

Location: Level 2 Exhibit Hall

Boosting Low Power Verification Methodology: Introducing Power-Aware Formal Property Verification into the Flow​

Presenter: Patrick Blestel

Type: Engineering Poster

Time: 12:15pm - 1:15pm PDT

Location: Level 2 Exhibit Hall

Improving Digital Design Performance and Area using DSO.ai​

Presenter: Massimo Bertoletti

Type: Engineering Poster

Time: 12:15pm - 1:15pm PDT

Location: Level 2 Exhibit Hall

Keeping the Guard Up with Security across the Board

Organizer: Sabya Das

Moderator: Sabya Das

Type: Engineering Special Session

Time: 1:30pm - 3:00pm PDT

Location: 2010, Level 2

Navigating 3D, Clock Trees, and Shared Learning

Session Chair: Igor Markov

Type: Research Manuscript

Time: 1:30pm - 3:00pm PDT

Location: 3006, Level 3