The introduction of USB4 v2 represents a significant milestone in high-speed data transfer technology for consumers. This new specification boasts a data transfer rate of 80 gigabits per second, doubling the speed of the preceding USB4 v1. USB4 v2 opens the doors for a new array of applications. Consider a system where a desktop or laptop is equipped with USB4 v2 ports. These ports facilitate connections to multiple high definition 6K or 4K monitors, ultra-high performance external SSD drives, and a hub for all legacy USB and various peripherals. All of these can be connected via a single USB type-C cable.

Moreover, USB4 v2 brings with it prospects beyond connectivity. Given the current expansion of artificial intelligence, the 80 gigabit per second connection promises potential benefits for processing at the edge. It could pave the way for next-generation AI accelerators, enabling more localized AI processing at the edge and lessening the reliance on cloud-based solutions.

This technical bulletin will explore the challenges and features associated with the transition from PAM-2 to PAM-3 encoding and the need for rigorous silicon characterization of USB4 v2 PHY IP. We will also examine the need of RX & TX equalization, the importance of backward compatibility, and the role of Forward Error Correction (FEC) as the demand for bandwidth increases.

PAM-3 Encoding requires Error Rate Reduction and complex TX Equalization

In previous USB standards, payloads were encoded from words to serialized binary data using two signal levels, using PAM-2 encoding -- also known as NRZ modulation. With PAM-3, words are encoded onto 3 different signal levels, as shown on Figure 1. For USB4 v2 transmit, 11 binary digits corresponding to 2048 different values are encoded to 7 ternary digits which can represent 2187 different values. Since only 2048 values are needed to convey data, some of the unused ternary values are used for control. This approach makes for some interesting, and un-usual digital design challenges.

USB4 v2 Gen4 signaling rate is 25.6Gtps per lane, which is equivalent to 40Gbps/lane and aggregating to 80Gbps when both TX/RX lanes of the USB Type-C® ecosystem are employed. To ensure robust data transfers, Forward Error Correction (FEC) is added to the binary data. This is followed by a binary to ternary conversion, scrambling, and pre-coding process. The ternary symbols are subsequently shaped using one of 42 distinct TX presets to provide the best possible adaptation to the USB Type-C channel, originally designed to support 10Gbps. A digital Feed Forward Equalization (FFE) and DAC (Digital-to-Analog Converter) transmitter design is used by the Synopsys USB4 v2 PHY IP to implement accurate TX presets.

Figure 1: PAM-3 TX eye showing wide open eyes and good symmetry from Synopsys USB4 v2 PHY IP

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Ensuring USB4 v2 Backwards Compatibility Requires Extensive Testing of Multiple Operating Modes

As for all previous USB standards, USB4 v2 implementations must maintain backwards compatibility. Because of this, silicon characterization is notably time-consuming, given the requirement to validate the TX eye quality across a myriad of TX presets for Gen4 data rate. Furthermore, this characterization process also mandated the evaluation of all previous USB standards as well as DisplayPort standards. Our decades on expertise in every generation of USB and DisplayPort designs help us ensure compliance and navigate the rigorous, meticulous testing of numerous configurations and operating modes the USB4 v2 PHY must support.  

Figure 2 shows the extensive array of operating modes that USB4 v2 PHY IP must support. Among these, is the USB4 v2 asymmetric mode, with 120Gbps TX and 40Gbps RX, capable of supporting multiple high resolution, high refresh-rate displays. While the USB4 v2 spec doesn’t mandate support for legacy ThunderboltTM 3, it is highly recommended for USB4 v2s hosts due to the large number of legacy Thunderbolt docking stations and peripherals in use.

Furthermore, in addition to the operating mode support through prior generations, the silicon characterization process must validate all operating modes across multiple combinations of silicon process, voltages, and temperatures (PVT). In practice, each individual test is performed 9 times for each of 5 process variations. Synopsys has developed advanced characterization automation that enables parallel testing of multiple test chips 24/7. 

Table 1: USB4 v2 PHY IP Operating Modes

USB4 v2 RX PAM-3: Decoding, Error Rate Reduction and RX Equalization

The process of receiving the USB4 v4 PAM-3 at 80Gbps is essentially the reverse process of the transmit:  7 ternary symbols are recovered and decoded to 11 binary data digits and control. This process involves the reverse of the steps mentioned earlier, including pre-coding removal, de-scrambling, ternary to binary conversion, and FEC decoding of the data stream. However, before the ternary symbols can be recovered, RX equalization must be applied. The eye at the receiver is completely closed due to channel losses, and Programmable Gain Amplifier, Continuous-Time-Linear-Equalizer (CTLE), Feed Forward Equalizer (FFE) and multi-tap Decision Feedback Equalizer (DFE) is used to open the eye and recover ternary symbols.

Figure 2: Typical calculated receive eye after RX equalization

PAM-3 Receiver Jitter Tolerance

Note that figure 2 does not show the actual eye as seen by the receiver. The USB4 v2 Compliance Test Specification and corresponding test procedures mandates the use of a known reference receiver, an embedded channel model and a SigTest tool to calculate an estimated receive eye. 

Synopsys design team’s uses Receiver Jitter Tolerance Testing to further validate the USB4 v2 PHY IP performance, employing advanced RX Equalization to further bolster data transfer robustness. The actual receiver quality is validated through RX Jitter tolerance testing. This involves the introduction of significant distortion in the form of jitter (which shifts the position of the eye of the symbol stream) to the signal to be received. The receiver under test attempts to recover the distorted signal and indicates how much receiver margin exists based on the extent of distortion that can be tolerated.

USB4 v2 also requires support for collecting statistics on FEC correctable and uncorrectable receive errors, as well as Receiver Lane Margining. When using Receiver Lane Margining, the vertical sampling position is shifted left or right from the nominal center of the eye and indicates how much margin exists. Likewise, the two horizontal slicing positions are shifted up or down. Together, this gives a good indication of the receiver robustness, but these results may prove challenging to interpret for non-experts. 

Figure 3 shows USB4 v2 PHY l Receiver Jitter Tolerance results for multiple combinations of Voltage and Temperature, showing a significant margin. This indicates the USB4 v2 PHY IP test chip is a robust implementation of the USB4 v2 specification.

Figure 3: Receiver Jitter Tolerance Results


The introduction of USB4 v2 presents a wide range of possibilities, with numerous applications yet to be developed. These applications could transform edge computing with AI. As the industry prepares for the future of USB4 v2 designs, the anticipation for supporting new, advanced use cases is high. To support new use cases USB needs to support faster data rates. USB4 v2 doubles the speed of USB4 to 80Gbps, or 120Gbps TX and 40Gbps RX. Deployment of USB4 v2 has started and designers need to understand some of the key implementation challenges of USB4 v2. Synopsys demonstrated the USB4 v2 PHY IP at DesignCon 2024 and has concluded preliminary characterization of the test chip. The Synopsys USB4 v2 PHY IP proven with our testchip is a key component for designing these new and exciting USB4 v2 products.


Synopsys is a major contributor to the development of the USB standards and a provider of the world’s most preferred and most widely used USB Controller and PHY IP from USB 1.1 to USB4 v2. Contact Synopsys for further information on how we can help kickstart your next USB design.


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