Logic Library Design for Significant Block PPA Improvements
Combining the benefits of the new TSMC 16FFC processes with optimized layout and innovative logic library circuit design provides design engineers who create blocks of digital logic from RTL through synthesis and place and route with several advantages. Routed block density is critical to saving both die area and saving power.
Efficient Layout for Minimum SoC Area and Minimum Total Power
Standard cell design is a complex process in which each circuit element, layout feature or tradeoff can have a major impact on a combination of performance, power, area (PPA) and manufacturability. Taking full advantage of process features such as continuous poly on diffusion edge (CPODE) enable routed blocks to be 5% smaller than a design using only poly on diffusion edge (PODE), for both minimum routed block area and minimum total power.
Optimizing register-to-register paths requires a rich standard cell library that includes the appropriate functions, drive strengths, and implementation variants. A rich set of optimized functions (NAND, NOR, AND, OR, inverter, buffers, XOR, XNOR, MUX, adders, compressors, etc.) are necessary for synthesis to create optimal circuits and optimized layout techniques are needed to get the most out of the latest routing algorithms to eliminate congestions. Advanced synthesis and place-and-route tools can take advantage of a rich set of drive strengths to optimally handle the different fan-outs and loads created by the design topology and physical distances between cells.
The setup plus the delay time of flip-flops is sometimes referred to as the “dead” or “black hole” time. Like clock uncertainty, this time eats into every clock cycle that could otherwise be doing useful computational work. Multiple sets of high-performance flip-flops are required to optimally manage this dead time. Delay-optimized flops (multi-delay flops) rapidly launch signals into critical path logic clusters and setup-optimized flops (multi-setup flops) capture registers to extend the available clock cycle in several increments. Synthesis and routing optimization tools can be effectively constrained to use these multi-setup/multi-delay flip-flop sets for maximum speed, resulting in a 15-20% performance improvement.
Memory Compiler Design for Significant PPA Improvements
Optimized for low power, high performance and high density, DesignWare® Memory Compilers offer advanced power management features such as light sleep, deep sleep, shut down and dual power rails, write assist, allowing designers to meet the stringent low-power requirements of today's SoCs. DesignWare Memory Compilers are closely coupled with the DesignWare STAR Memory System™, providing an integrated embedded memory test solution to detect and repair manufacturing faults for the highest possible yield with least impact on chip area. DesignWare Memory Compilers are silicon-proven with billions of chips shipping in volume, enabling designers to reduce risk and speed time-to-market.