By: Ken Brock, Product Marketing Manager, Synopsys
TSMC recently released its fourth major 16nm process into volume production—16FFC (16nm FinFET Compact). This process provides an easy migration from 28nm processes along with significant performance, power and area advantages. To develop the most competitive system-on-chips (SoCs) in this process, designers must choose optimized foundation IP building blocks (embedded memories and standard cell libraries) to achieve the highest SoC performance with lowest power and area. With the combination of the 16FFC process and the right foundation IP, designers can develop SoCs for applications from high-end green servers and network processors to ultra-low power mobile devices, consumer products, and wearables-and everything in-between.
This article describes seven ways designers can take advantage of this new process with the most advanced logic library and memory compiler technology to optimize the performance, power and area of their SoCs.
- Designers can improve SoC area by taking advantage of the Moore’s law scaling of 16nm as compared to 28nm.
- FinFETs provide higher saturation currents per unit area that can be turned into improved performance through different circuit topologies that enables the use of shorter logic cells to close critical timing paths.
- FinFETs have much less leakage as compared to 28nm but consume relative higher dynamic power due to increased input capacitance of the fins.
- Standard cell architectures can take advantage of innovative process technology (continuous poly) to produce the densest layouts for both area and power savings aided by physical design tools co-optimized with logic libraries.
- Routable high fan-in standard cells and new sequential cells with multi-delay, multi-setup and multi-bit flip-flops (MBFF) enable designers to optimize their processor cores for both performance and power.
- A broad array of memory compilers using multiple bitcells with multiple periphery VTs and innovative power management features.
- The combination of innovative process technology and library design capabilities along with the latest EDA tool innovations and flows enable SoC designers to use their design skills to develop the highest performance designs with the lowest die cost and consuming the lowest power.
As part of Moore’s Law and classic Dennard scaling, the 16FFC process offers a smaller transistor pitch (contacted poly pitch or CPP), smaller interconnect metal pitch (wire to wire, via to wire and via to via) for routing and a smaller bitcells that provide a basic area reduction. Optimized IP layout innovations can take advantage of these smaller design rules while addressing challenges of 16nm that include higher wire resistance due to thin wires, and associated electro-migration concerns for signal wires and for the power grid. These must be addressed both in IP architecture and IP validation. As seen in Figure 1, with optimized foundation IP, 16FFC provides greater than two times the area benefits and greater than 30% performance improvements as compared to 28nm.