Scalability, Security and Reliability with One-Time Programmable Non-Volatile Memory

Krishna Balachandran, Product Marketing Manager, Synopsys

Non-Volatile Memory (NVM) is used for persistent data and secure code storage in a wide range of electronic systems in automotive, mil-aero, power management IC (PMIC), mobile, and Internet of Things (IoT) markets. NVM comes in different flavors including multiple-time programmable (MTP), few-time programmable (FTP), and one-time programmable (OTP). When determining the ideal NVM solution, designers must consider scalability, reliability, product specifications, and availability on the target semiconductor manufacturing process. Other considerations like bit count, endurance, access time, programming time, temperature, and operation voltage also come into play as designers make trade-offs to find a solution that best serves their needs.

Many applications do not need the re-programmability in the field and OTP has quickly become the embedded NVM of choice due to its broad availability in standard Complementary Metal-Oxide-Semiconductor (CMOS) processes, scalability, high reliability, and security. OTP NVM targets a wide range of applications ranging from storing a few bits of authentication information to product configuration, calibration or even firmware for today’s system-on-chip (SoC) designs. OTP NVM can be based on the floating-gate, eFuse, or antiFuse technology, each with its own unique advantages. This article describes the advantages of OTP NVM, based on antiFuse technology, as the most secure and reliable embedded NVM solution for applications. 

Floating-Gate OTP NVM

Traditional OTP NVMs were based on floating-gate technology which traps the charge on the floating gate to program the device and depletes the charge to erase it. Charge-trapping and depletion require applying high voltages to the device, and creating a floating gate and insulating oxide require extra masks and manufacturing steps to the standard CMOS process. Floating-gate OTP NVM scales well in mature process nodes down to 130-nm but requires additional design efforts and becomes uncompetitive in area and performance at smaller process technologies including FinFETs. For example, today floating gate NVM is available in 40-nm process with ongoing efforts to bring it to market in 28-nm process, however, the extra processing steps and masks impact the cost of manufacturing and testing for cost-sensitive applications. Additionally, exposure to Ultra Violet (UV) light or radiation can erase the data in a floating-gate OTP NVM, giving hackers the opportunity to manipulate the charge stored by applying high voltages or temperatures to an already programmed device to gain unauthorized entry into an electronic system.

Electric-Fuse OTP NVM

Electric-fuse (eFuse) OTP NVM became mainstream in the sub-micron era since they scaled across foundry process technologies better than floating-gate OTP NVM. eFuse OTP NVMs were initially polysilicon-based, but have been replaced by metal fuses in smaller process technologies. They are based on the principle of electromigration, which programs the fuses at the time of manufacturing. By default, metal-based eFuse OTP NVMs are continuous metal shapes etched on the silicon surface. Applying high voltages to selected fuse metal lines causes electromigration and subsequently disconnects (opens) the metal lines. Since there is no trapped charge, it is impossible to easily reverse engineer the content of an eFuse. eFuses in advanced and FinFET process technologies do not scale well and when larger capacity OTP NVMs are needed, the area can be considerable. eFuses suffer from high leakage current in the standby mode and from re-growth issues where the same electromigration that causes metal lines to disconnect can also result in metal lines to unintentionally connect again, changing the data intended to be stored. Due to these reasons, foundries and semiconductor IC designers are leaning towards alternatives to eFuse technology.

AntiFuse OTP NVM

AntiFuse OTP NVM went into widespread commercial production about 10 years ago. The underlying technology for antiFuse OTP NVM is oxide breakdown, which is fundamentally different from that of the floating-gate or eFuse-based OTP. No special masks or process steps are required to manufacture the NVM device. In a standard CMOS process, the antiFuse OTP NVM uses the same rules as logic devices for electrical and layout design, providing scalability at the most advanced nodes, down to 7-nm. Fundamentally, antiFuse technology relies on using both the thinner core oxide and the thicker I/O oxide available in standard CMOS processes to create a conducting path through the core oxide when programmed. Programming is achieved by applying a high voltage on the gate which causes the thinner core oxide to break down. Absence of the high voltage on the gate leaves the device unprogrammed. Since no changes are required to the manufacturing process, the antiFuse OTP reaps the benefit of the same yield and reliability as a standard CMOS process. Therefore, with foundries constantly tuning their manufacturing processes, antiFuse OTP NVMs can be implemented in the latest FinFET processes without any reliability concerns.

Once programmed by oxide breakdown, there is no going back. antiFuse OTP NVMs do not suffer from the re-growth issues sometimes seen with eFuses. Since no charge is involved, it is not easily susceptible to any passive or invasive security attacks attempted by altering the voltage or temperature. The oxide breakdown is also not visible with a Scanning Electron Microscope (SEM) and it is impossible to tell the difference visually between a programmed and an unprogrammed cell within an antiFuse OTP NVM. Antifuse OTP NVMs are also area optimized due to their high scalability, and they deliver the lowest leakage power amongst all the OTP NVM types. Programming time and read-access time are also very competitive and meet the demands of many high-performance, low power systems in design today.

AntiFuse OTP NVM Applications

When based on antiFuse technology vs. floating-gate or eFuse, NVM OTP offers high process scalability, Megabit macro capacity, low active read power, high voltage, and temperature tolerance, as well as high security. AntiFuse OTP NVM replaces floating-gate or eFuse technologies for tasks such as secure key storage, device IDs, analog/sensor trimming and calibration, and code storage, each requiring different range of bit counts from a few bits to multi megabits, as show in Figure 1. 

Figure 1: The vast portfolio of AntiFuse OTP NVM applications

AntiFuse OTP NVM Advantages

Battery life is important for devices such as wearables and smart phones where consumers expect the battery to last for days or even months. Since antiFuse OTP NVM supports very low read power, it makes it ideal for battery operated devices requiring low-power consumption during active (read operations) and standby modes. OTP NVM is also the first circuit to become active as power supplies ramp up. SoCs for battery operated devices can incorporate OTP NVM that scales across a wide range of foundry processes, including FinFETs, to take advantage of the process technologies’ power, performance, and area benefits.

Security is a key requirement when going from edge to cloud, as devices are exposed to malicious attacks from all around the globe. Some of these devices function as safety-critical systems in automotive, mil-aero, and medical applications where wired and wireless connectivity and data accuracy are vital. Mobile and home entertainment devices require user authentication to maintain the integrity of financial transactions or to provide conditional access. OTP NVM supports the highest security options both for stored memory data and for reading or writing memory data. Properly designed antiFuse OTP NVM can easily thwart attempts to reverse engineer, making its content safe.

Reliability is another key requirement, especially in harsh environments for automotive and industrial applications. When properly qualified at high operating temperatures of up to 150°C and even 175°C, and tested for Early Life Failure Rates, antiFuse OTP NVM is the best choice for reliable operation for the life of the product.   

DesignWare OTP NVM IP Solutions

Built on antiFuse technology, Synopsys DesignWare OTP NVM IP Portfolio offers a secure and flexible embedded memory solution in standard CMOS without requiring additional process or mask steps. Its patented 1T and 2T antiFuse bitcells offer small silicon footprint, and its built-in security features protect against active and passive attacks, tampering, hacking, and reverse engineering. The customizable macros allow design flexibility for the target application to execute code storage, security, trimming, calibration, and configuration functions. Qualified for automotive AEC-Q100 grade 0 and 1 temperatures, the DesignWare OTP NVM IP accelerates SoC-level development. It is available across multiple foundries including TSMC, SMIC, UMC, and GLOBALFOUNDRIES, supporting processes from 180-nm to 7-nm FinFET. With capacity targeting Megabit OTP needs, Synopsys’ OTP NVM IP provides a lower cost alternative to ROM, embedded Flash, and serial EEPROM or Flash. Synopsys’ antiFuse OTP NVMs have been in mass production in a broad range of systems including sensors, display drivers, power management ICs, connected and wireless devices, home entertainment systems, high-end wearables, mobile, automotive infotainment and advanced driver assist systems (ADAS), and highly secure military and aerospace applications.