Synopsys DesignWare IP R&D teams who develop cores like MIPI, HDMI, and USB IP face the same distribution issues as Synopsys customers and must comply with security and license restrictions but at the same time provide an easy way to integrate and validate IP blocks. The Synopsys HAPS series has been a vehicle for internal validation, protocol compliance testing at plug-fest events, and distribution of example implementations to customers for several years. An organization may “publish” IP as raw RTL source, hardened into FPGA-based hardware, or deployed as FPGA device program/bitstream images. Each has advantages and disadvantages and a modern FPGA-based prototyping system like HAPS-70 supports IP variations no matter the degree of hardening. The first off-the-shelf DesignWare IP implementations using the new HAPS-70 series are projected for availability in the fourth quarter of 2013.
The HAPS-70 system is the most modular and I/O intensive system yet designed by Synopsys after several generations of PCB, connector, and electromechanical refinements made over the years. To address the spectrum of capacity demands HAPS-70 is offered in nine different configurations from 12M to 144M ASIC gates of capacity. The HAPS-70 S24 shown in the photo below is comprised of two PCB modules each with a single Xilinx Virtex-7 2000T device.