Error correction support is included for all the internal memories: L1 cache, L2 cache, close coupled memory, and the MMU Joint Translation Lookaside Buffers (JTLBs). The error correcting code (ECC) also protects the interface buses to the rest of the SoC. The ECC capability can detect and correct single-bit errors, and can detect a double-bit error. A double-bit error that can’t be corrected is handled by system exception, which can lead to a controlled condition within the system. The ECC logic is non-intrusive to the processor pipeline, so performance is maintained.
The lockstep monitoring on the HS38x4 is implemented with a shadow secondary core that is used for comparison to the main core. The operation of the shadow core can be delayed from the main core to avoid duplicate common-cause facilities. The safety monitor that is connected to both the main and shadow cores continuously runs diagnostics with compare logic to verify functionality and report errors to the system. The implementation supports all of the standard features of a single core, including debugger access to the main core and verification of the access in the shadow core.
The safety manager that is outside of the HS38x4 core (shown to the left of the core in Figure 1) gets input from the safety monitor in the HS processor and from other sources in the SoC and reports these to the host processor. The safety manager is implemented with dual-core lockstep processor to protect against problem conditions in the manager. It also has full ECC and its own watchdog timer. The safety manager controls the HS38x4 cluster “safety” bring-up and the boot-time LBIST and MBIST control. The safety manager can be implemented with either an ARC HS or ARC EM processor, depending on the speed that it needs to be clocked.