To successfully test with the Gold Tree, the Host is connected to the Gold Tree, all the drivers load correctly, and all the peripherals operate as expected. For example, during the test, the Host must be able to print from the printer, accept input from the keyboard and mouse, start the webcam video stream, play music on the headphones, and read and write to all the flash drives.
As of Fall 2016, there are a few USB 3.1 Gen 2 peripherals available for interoperability testing. As USB 3.1 Gen 2 Hubs become available, a USB 3.1 Gen 2 Gold Tree tester will be created. For now, designers need to use USB 3.1 Gen 2 interoperability in addition to USB 3.0 Gold Tree testing.
3. Interoperability testing
Interoperability of USB 3.1 Hosts requires extensive hardware testing. The most challenging of these is testing with peripherals at different speeds including USB 2.0 (Hi-Speed, Full Speed, and Low Speed), USB 3.1 Gen 1 (5 Gbps) and USB 3.1 Gen 2 (10 Gbps). The USB 3.1 Gen 2 Host must connect directly to each 2.0 peripheral and demonstrate operation.
The Platform Interoperability Lab (PIL) run by the USB-IF and third-party testing facilities use a well-defined set of peripherals for interoperability testing. Interoperability testing at a Plugfest uses a range of new peripherals, and the Host must function with 90% of the peripherals made available.
Interoperability testing of the controller also exercises interoperability testing of the PHY. Electrically, this also makes a design more robust for the PHY, the controller, and the entire solution.
4. Certification checklist completion
The USB-IF requires all applicants complete a checklist. This is for system makers. The checklist actually helps designers check to see that their design meets requirements that are not tested whether through USB or electrical tests. It is self-reporting, but guides the product makers to a better product when followed and completed.
5. Electrical testing
Electrical testing is required at the system level for all products and is intended to ensure that the physical layer (PHY) can transmit and receive data across a cable. It’s critical for a Host because the quality of the peripheral PHYs it connects to varies significantly. In fact, a good PHY can overcome some poor cabling or poor peripheral PHYs. At 10 Gbps, this test is more important because the cables are now up to 2m long.
A good example of an electrical test is the Receive Jitter Tolerance test. In an SoC, the USB may be transferring data at the same time a PCI Express or WiFi transmission is occurring. The analog parts of those generate noise on the USB receiver, creating errors in receiving data. This noise is measured as jitter. During testing, the system must generate noise and demonstrate a bit error rate of less than 10-10. The lower bit error rate means the data is received and read accurately, minimizing retries and maximizing throughput. Passing this test ensures the PHY operates so that it can receive data accurately and with good overall throughput.
6. xHCI Host Testing
Host controllers require an additional set of tests. To obtain them, a company must go to Intel, and sign a special agreement to obtain the test suite. The tests take up to three calendar weeks to run and extensively exercise the controller.
USB Host certification is the most extensive USB certification process, and the most difficult to obtain. Most PC makers are able to obtain certification because the PC chipset providers have completed certification in advance. As long as the PC makers follow the guidance from the PC chipset providers, their system will likely pass compliance testing. For SoC developers, it's tougher. They need to ensure their entire chip works, and the IP has already passed the Host certification testing. They may or may not have the resources and expertise of the PC chipmaker. Synopsys is the only IP vendor to have earned USB 3.1 Gen2 certification for its Host and Device IP solutions, which include DesignWare USB 3.1 Gen2 controllers and PHYs. Using compliant, certified USB IP lowers integration risk, helps projects tape out on schedule, and supports first-silicon success for improved time-to-market.