The safety islands are based on ARC EM processors with hardware features such as ECC and a programmable watchdog timer to detect system failures as well as runtime faults. The processors include a lockstep interface that is used by the integrated safety monitor to compare outputs and detect if a fault has occurred. The ARC EM Safety Islands are supported by comprehensive safety documentation, including FMEDA reports that facilitate chip- and system-level ISO 26262 ASIL D compliance. In addition, the MetaWare Toolkit for Safety eases the development, debugging, and optimization of ISO 26262 compliant software targeting ARC processors.
Like the ARC EM processors themselves, the safety islands are configurable and extensible to meet the unique safety, performance, and area requirements of each target application, including advanced driver assistance systems (ADAS), radar and sensor processing. The cores in the EM Safety Island can also operate in an independent dual-core mode to provide additional performance in applications that do not require lockstep execution, such as those targeting ASIL B safety standards. In addition, the processors offer options including a memory protection unit (MPU) and a microDMA engine to meet system-level protection and latency requirements (Figure 1). These options are tightly-coupled to each processor core to provide redundancy and further reduce single points of failure in the IC. The self-checking safety monitor includes time diversity with parity to protect system integrity if noise pulses hit both cores simultaneously.
Meeting the requirements of automotive safety-critical applications adds to the cost, complexity, and timeline of designing ICs. By selecting pre-verified ASIL D Ready certified processor IP solutions that are also configurable, like the ARC EM Safety Islands, designers will be able to meet aggressive area and time-to-market targets with a highly competitive automotive product.