Process technologies play a key role in determining which implementation is most advantageous for a target application. The standalone RF transceiver uses legacy nodes such as 180-nm. The wireless network processor, where the wireless protocol stack is embedded into the RF transceiver, leverages the mature 90-nm node. The 40-nm and 55-nm technology nodes are becoming popular in monolithic wireless solutions due to the combination of embedded flash and highly available mixed signal IP, including wireless IP. The 28-nm node is expected to be viable for similar monolithic wireless SoC solutions where the protocol stack, RF transceiver, and application code is integrated into a single SoC.
The combo wireless IC chipset solution is still a prevalent architecture for mobile application processors leveraging the most aggressive process nodes available to optimize die size and cost. These systems have unlimited off-chip memory which gives programmers more resources, but the number of total chips in the system can be as many as three, versus one or two chips in the other three implementations. This clearly demonstrates how wireless integration can be beneficial when the process nodes and available IP solutions align, and why the fully integrated wireless SoC architecture will become pervasive.
Current wearable designs, such as fitness bands, that only implement Bluetooth low energy for wireless connectivity, consist of an SoC connected to an external Bluetooth low energy IC via a UART or I2C bus. Similarly, virtual reality goggles use a standard Bluetooth wireless network processor to communicate with gaming controllers. External Bluetooth low energy chipsets are also found in smart home products such as door locks, lighting, and indoor location beacons. These examples show opportunities for wireless integration into SoCs already in the system for additional cost savings.
If higher bandwidth wireless technologies, such as WiFi, are also included in the design, a wireless combo chip solution is used with multiple wireless technologies, a processor and external memories. For example, augmented reality goggles require more processing power so designers leverage a similar implementation as in the mobile platform.
Wireless is replacing many functions that traditionally were wired. Bluetooth low energy in particular is being used for diagnostics and passing low bandwidth information where UART, I2C, SPI, and USB had traditionally been used.
Advantages of Integrating Wireless Technology in a Single SoC
Now that we’ve identified the opportunities for wireless integration into a single SoC, let’s look at the advantages and disadvantages.
Wireless network processors, such as standalone Bluetooth low energy solutions, have been consistently utilized in certified systems, easing designers’ module certification processes. These standalone Bluetooth low energy solutions not only ease certification but provides proven reliable connectivity with common system design methodologies in regards to items such as antennas.
A monolithic solution offers greater benefits that include lower power, lower costs, lower latency, and smaller footprints, pushing the market to start adopting and designing fully monolithic wireless SoCs. It is expected that data sent over the AMBA® AHB® bus versus the SPI bus can reduce latency by 5 to 10 cycles, enabling longer idle times for the processor saving power. In fact, in a recently published report from Microsoft Wireless Power Research, "The parameters that dominated power consumption were not the active or sleep currents but rather the time required to reconnect after a sleep cycle and to what extent the RF module slept".
Beyond power and latency improvements, wireless integration enables the removal of complete chip sets, reducing packaging costs and the required additional pads and power management IP. This can save over $0.15 in packaging costs and 20-30 extra pads that are required to support the additional wireless network processor. These savings, in conjunction with removing duplications of power management and a reduced PCB footprint, make the total system cost savings very attractive.
As noted in the teardown.com report, multiple wireless ICs are found in a system like virtual reality goggles. Bluetooth and WiFi have commonly been combined in a single chip but requirements for these wireless technologies are very different. WiFi supports high bandwidth, whereas Bluetooth low energy minimizes power. WiFi supports speeds up to 300 Mbps, uses well over 40-100 microWatts of receive and transmit power and a sizable memory requirement. To support the WiFi throughput, the SoC must operate at appropriate voltages per the target process technology. Alternatively, Bluetooth low energy supports 2 Mbps in Bluetooth 5 and uses less than 10 microWatts of transmit and receive power, with much smaller memory footprints and lower voltages such as 0.9V in the newest 40-nm and 55-nm ultra-low-power processes.
The advantages of integrating Bluetooth low energy are clear, and monolithic wireless SoC implementations are expected to become common in the near future. The advantages become greater for IoT SoCs that require extremely low power consumption on 55-nm and 40-nm technologies. Such IoT SoCs also leverage power management techniques, DC-DC down-converters and use thick oxide technologies to reduce the active power and the leakage power even more.
Complete Bluetooth Low Energy PHY and Link Layer IP
Synopsys offers a wide range of wireless and analog IP options for 5G, WiFi and LTE for cellular, wireless 802.15.4 and Bluetooth technologies with optimized analog front-ends, data converters and a complete Bluetooth low energy IP solution with PHYs and Link Layer IP.
Synopsys’ complete DesignWare Bluetooth IP solution with PHY and Link Layer is compliant with the latest Bluetooth specification with the PHY supporting Bluetooth 5 and the IEEE 802.15.4 standard for connectivity over Zigbee and Thread networks. The Link Layer enables secure wireless connections with integrated data encryption and random number generation, allows up to eight simultaneous connections in a single instantiation, and offers validated interoperability with third-party software stacks and processors. The PHY operates at a sub-one-volt supply for extended battery life and includes an integrated on-chip transceiver matching network and single pin-to-antenna interface and voltage regulators to reduce BOM cost and simplify the system design and integration. The Bluetooth PHY is available on 180-nm, 55-nm and 40-nm process nodes allowing designers to also take advantage of the advanced processes’ power, area and performance benefits. The PHY on 55-nm and 40-nm are especially advantageous for IoT SoC designers due to the processes’ extremely low power and area benefits.
The DesignWare Bluetooth Low Energy IP solution is qualified by the Bluetooth Special Interest Group (SIG) which is critical for designer success. The IP has gone through a rigorous validation process from a complete design verification flow to full characterization of PVT corners and interoperability with the ecosystem.
The advantages of wireless integration into an IoT SoC is paramount and Synopsys has the expertise, silicon-proven IP and proven track record to help designers enable efficient wireless connectivity for IoT SoCs.