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The growing use of a variety of sensors in edge devices – from wearables to virtual assistants to automotive radar/LiDAR – requires SoCs to have an optimal balance of DSP performance and low power/area. In addition, SoC developers must be able to easily scale their hardware architectures to handle a varying number of data streams while preserving their software investment; it’s just not practical to start over when the current or next design requires a higher or lower level of throughput.
In this Synopsys webinar we will highlight some of the sensor fusion applications driving the need for more efficient digital signal processing, often combining classical filtering operations and AI-based decision making. Featuring the Synopsys ARC® VPX DSP family, we will explain key functions that can be optimized to handle a spectrum of sensor fusion workloads, while adhering to a single programming environment.
Principal R&D Engineer
Pieter van der Wolf is a Principal R&D Engineer at Synopsys. He received his MSc and PhD degrees in Electrical Engineering from the Delft University of Technology. He was an Associate Professor at the Delft University of Technology before joining Philips Research in 1996. In 2006 he joined NXP Semiconductors when it was spun out of Philips Electronics. In 2009 he joined Virage Logic, which was subsequently acquired by Synopsys. He has worked on a broad range of topics including multi-processor architectures and system design methodologies.