If you are designing chips for high-performance computing (HPC) and data center applications, bandwidth is, of course, a key consideration. However, as data centers get bigger and the required compute power increases, keeping power consumption to a minimum becomes a priority. In addition to power, latency is another key concern for HPC and data center SoC designers as access to the available memory pool is becoming a bottleneck and must be allowed in nanoseconds.
Attend this webinar to learn more about some of the power reduction mechanisms, such as L0p power state, clock power gating, and static and dynamic voltage scaling, as well as datapath latency reduction techniques in the PCIe 6.0 and CXL 2.0/3.0 specifications.
Learn how to use tailored IP to make latency and power tradeoffs to achieve the optimal results for your HPC and data center SoCs.