Navigating Between DDR5, LPDDR5, and HBM2/2E IP to Meet Your Design Goals

In this webinar, our SVP, John Koeter, highlights the different market trends and memory use cases for high-performance computing SoC (HPC) designs. Our product expert, Graham Allan, follows by looking into the specific features of DDR5, LPDDR5, and HBM2E IP for high-performance computing SoCs. Graham highlights different considerations such as capacity, power-efficiency, and bandwidth that designers must focus on when navigating between memory options.  

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John Koeter, SVP of Marketing and Strategy for IP

John Koeter joined Synopsys in 1998 and is currently Senior Vice President of Marketing and Strategy for IP. Before coming to Synopsys, Mr. Koeter held marketing, engineering, and corporate application engineering positions with Texas Instruments and Advanced Micro Devices.

Graham Allan, Sr. Product Manager for Memory Interface IP

Graham Allan brings over 25 years of experience in the memory industry. Graham has spoken at numerous industry conferences and is a significant contributor to the SDRAM, DDR and DDR2 JEDEC memory standards. He currently holds 25 issued patents in the area of memory design.