Executive and Expert Access: Accelerating High-Performance Computing SoC Designs with Synopsys IP

A Webinar Series

Don’t miss this opportunity to hear from Synopsys’ IP senior executives and product experts on how to accelerate your high-performance computing SoC designs. Find out about the latest market trends that will help you make important design decisions. Learn how specific features of Synopsys’ IP enables you to achieve the required functionality for your chip and deliver competitive products to market faster. 

The New Frontier of Die-to-Die Interface IP: What You Need to Know for Silicon Success
Original broadcast: June 16, 2020

Learn about emerging use cases requiring die-to-die connectivity. Find out how to make tradeoffs between bandwidth, power, and latency with Synopsys' 112G per lane SerDes-based PHYs for USR/XSR links or parallel-based PHYs with data rates up to 4Gb/s per pin.

Navigating Between DDR5, LPDDR5, and HBM2/2E IP to Meet Your Design Goals
Original broadcast: June 23, 2020

Learn about the DDR5, LPDDR5 and HBM2/2E standards’ key features such as speed, clocking, operating voltage, DRAM topologies, and more. Hear the advantages and find out how to select the ideal memory technology to meet your target applications’ requirements.

Keys to Achieving Maximum Throughput and Lowest Latency for PCI Express 5.0 and CXL Designs
Original broadcast: June 30, 2020

Find out about an easier migration path to PCIe 5.0 design, overcoming challenges such as signal integrity, packaging issues, and timing closure. Learn how Synopsys' CXL IP supports different CXL configurations to help meet the design requirements of high-performance computing SoCs requiring cache coherency.

Agenda

  • Senior executive presentation (including Q&A)                10 minutes       
  • Product expert presentation (including Q&A)                   40 minutes
  • Q&A                                                                                          10 minutes

Speakers

John Koeter, Sr. VP of Marketing and Strategy

Executive Speaker: All Three Webinars

John Koeter joined Synopsys in 1998 and is currently Senior Vice President of Marketing and Strategy for IP. Before coming to Synopsys, Mr. Koeter held marketing, engineering, and corporate application engineering positions with Texas Instruments and Advanced Micro Devices.

Manmeet Walia, Sr. Product Manager

Product Expert Speaker: The New Frontier of Die-to-Die Connectivity: What You Need to Know for Silicon Success

Manmeet Walia brings over 18 years of experience in product management and system engineering covering ASSP, ASIC, and IP products for broad range of applications. Manmeet holds a Master of Science degree in Electrical Engineering from University of Toledo, and an MBA from San Diego State University.

Graham Allan, Sr. Product Manager

Product Expert Speaker: Navigating Between DDR5, LPDDR5, and HBM2/2E IP to Meet Your Design Goals

Graham Allan brings over 25 years of experience in the memory industry. Graham has spoken at numerous industry conferences and is a significant contributor to the SDRAM, DDR and DDR2 JEDEC memory standards. He currently holds 25 issued patents in the area of memory design.

Gary Ruggles, Sr. Product Manager

Product Expert Speaker: Keys to Achieving Maximum Throughput and Lowest Latency for PCI Express 5.0 and CXL Designs

Gary Ruggles brings over 25 years of experience in electronics and integrated circuit design. Gary began his career as Assistant Professor of Electrical and Computer Engineering at North Carolina State University, where he taught courses in Solid State Physics and VLSI Processing.