Hsinchu
Synopsys Taiwan Co., Ltd.
4F-1, #28, Tai-Yuan Street
Chupei City
Hsinchu Hsien 302, Taiwan
Tel: +886-3-552-5880
Fax: +886-3-552-5881
tw_feedback@synopsys.com
Taipei
Synopsys Taiwan Co., Ltd.
Room 3108, 31F
333 Keelung Road, Section 1
Taipei 110, Taiwan
Tel: +886-2-2345-3020
Fax: +886-2-2757-6009
tw_feedback@synopsys.com
Hsinchu
Synopsys Taiwan Co., Ltd.
No. 25, Industry East Road IV
Science-Based Industrial Park
300 Hsinchu, Taiwan
Tel: +886-3-579-4567
Fax: +886-3-579-9000
tw_feedback@synopsys.com
To register for a course and view full course descriptions, visit the new Taiwan Training page
** Synopsys reserves the right to cancel or re-schedule the workshops **
Daily Class Time: 9:30 a.m. - 5:00 p.m.
Download Training Schedule (PDF)
Workshop Schedule 2016
| Date | Location | Workshop | Cost |
| Nov 24-25 | Hsinchu | Star-RC | NTD 10,000 |
| Dec 07-09 | Hsinchu | SystemVerilog Testbench | NTD 15,000 |
| Dec 15-16 | Hsinchu | Hspice Essentials | NTD 10,000 |
Workshop Schedule 2017
| Date | Location | Workshop | Cost |
| Jan 10-11 | Taipei | CustomSim-XA Essentials and Mixed Signal Verification (XA-VCS) | NTD10,000 |
| Jan 11-13 | Hsinchu | Design Compiler | NTD15,000 |
| Jan 12-13 | Taipei | PrimeRail | NTD10,000 |
| Jan 17-18 | Hsinchu | SiliconSmart 101 | NTD10,000 |
| Jan 18-20 | Taipei | IC Compiler Block-Level Implementation | NTD15,000 |
| Jan 19-20 | Hsinchu | Formality (Functional Equivalence Checking) | NTD10,000 |
| Feb 08-10 | Hsinchu | UVM 1.2 | NTD15,000 |
| Feb 09-10 | Taipei | Star-RC | NTD10,000 |
| Feb 15-17 | Hsinchu | IC Compiler II: Block-level Implementation | NTD15,000 |
| Feb 22-24 | Hsinchu | PrimeTime | NTD15,000 |
| Mar 10 | Hsinchu | FineSim Essentials | NTD5,000 |
| Mar 15-17 | Hsinchu | DFT Compiler | NTD15,000 |
| Mar 22 | Hsinchu | SystemVerilog Assertions | NTD5,000 |
| Mar 23-24 | Hsinchu | IC Compiler II: SoC Design Planning | NTD10,000 |
| Apr 11-12 | Hsinchu | Star-RC | NTD10,000 |
| Apr 12-14 | Taipei | SystemVerilog Testbench | NTD15,000 |
| Apr 13-14 | Hsinchu | PrimeRail | NTD10,000 |
| Apr 19-21 | Hsinchu | TetraMAX | NTD15,000 |
| Apr 26-28 | Hsinchu | IC Compiler II: Block-level Implementation | NTD15,000 |
| May 10-12 | Taipei | Design Compiler | NTD15,000 |
| May 16 | Hsinchu | Power-Aware Verification with VCS-NLP and UPF | NTD5,000 |
| May 17 | Hsinchu | Design Compiler 2 : Low Power | NTD5,000 |
| May 18-19 | Taipei | Formality (Functional Equivalence Checking) | NTD10,000 |
| May 23-25 | Hsinchu | IC Compiler Block-Level Implementation | NTD15,000 |
| May 24-25 | Taipei | Hspice Essentials | NTD10,000 |
| Jun 07-09 | Taipei | UVM 1.2 | NTD15,000 |
| Jun 14-15 | Taipei | Star-RC | NTD10,000 |
| Jun 15-16 | Hsinchu | CustomSim-XA Essentials and Mixed Signal Verification (XA-VCS) | NTD10,000 |
| Jun 21-23 | Hsinchu | PrimeTime | NTD15,000 |
| Jun 28-30 | Hsinchu | IC Compiler II: Block-level Implementation | NTD15,000 |
| Jul 20-21 | Taipei | SiliconSmart 101 | NTD10,000 |
| July 26-28 | Hsinchu | SystemVerilog Testbench | NTD15,000 |
| Aug 09-11 | Taipei | IC Compiler Block-Level Implementation | NTD15,000 |
| Aug 16-18 | Hsinchu | DFT Compiler | NTD15,000 |
| Aug 22-23 | Hsinchu | Star-RC | NTD10,000 |
| Aug 24-25 | Hsinchu | PrimeRail | NTD10,000 |
| Sep 06-08 | Hsinchu | TetraMAX | NTD15,000 |
| Sep 13-15 | Hsinchu | Design Compiler | NTD15,000 |
| Sep 15 | Taipei | FineSim Essentials | NTD5,000 |
| Sep 20-22 | Hsinchu | UVM 1.2 | NTD15,000 |
| Sep 26-27 | Hsinchu | Formality (Functional Equivalence Checking) | NTD10,000 |
| Oct 18-20 | Taipei | PrimeTime | NTD15,000 |
| Oct 18-20 | Hsinchu | IC Compiler Block-Level Implementation | NTD15,000 |
| Oct 26-27 | Hsinchu | Hspice Essentials | NTD10,000 |