Viettel, the largest mobile network operator in Vietnam, has big ambitions with 5G technology at the system, equipment, and SoC levels. As the R&D arm of Viettel, Viettel High Tech develops full 5G network architecture systems: devices, radio access network (RAN), transmission network, and core network. This makes Vietnam one of the few countries to produce 5G equipment.
Viettel High Tech had been working on the design of a 5G digital front-end SoC for a gNB 3GPP 5G base station. The engineering team needed to accelerate their time to market for a competitive advantage. In fact, facing a short product development window is not uncommon in this sector. Many organizations began developing their solutions while the 5G standard was still immature, creating the need to keep up with a changing standard without delaying product readiness.
To streamline the process for developing specialized processors for their 5G SoC, the Viettel High Tech team used Synopsys ASIP Designer™, a tool suite that automates and speeds up the process of designing application-specific instruction-set processors (ASIPs).
“ASIP Designer accelerated the design process of Viettel’s first 5G digital front-end SoC to save time and to achieve the desired performance,” noted Le-Thai Ha, Ph.D., a principal engineer at Viettel High Tech. “With ASIP Designer, we can easily adapt designs to new versions of our 5G algorithms with minor changes in the architecture, size, and power consumption. The compiler-in-the-loop and synthesis-in-the-loop design flows that come with ASIP Designer save us months in multiple iterations of changes and optimization. Furthermore, ASIP Designer opens multiple rooms and options for us to optimize the 5G signal processing stream during the SoC development phase and after silicon readiness. We wouldn’t have been able to achieve this flexibility with hard-wired designs.”
Read on for more details about how the Viettel team worked with Synopsys to achieve their goals for their 5G design.