Synopsys Formal Consulting Services

The Synopsys Formal Consulting Services team is made up of world-class formal experts with access to leading-edge formal technologies, such as formal property verification, datapath verification, security and functional safety verification. The team has completed over 25 projects in the last 5 years with experience verifying some of the most challenging blocks in an SoC: CPU, GPU, AI chips, protocol bridge, cache coherence, power controller, FPU, CNN accelerators, DDR, USB, DMA, and more. 

Synopsys Formal Consulting Services offer various options to suit the unique needs of our customers. From formal methodology training to turn-key projects, customers can customize and define the projects through a statement of work (SOW). A licensed Verification CoStart Service is also available. 

Turn-Key Projects - Synopsys VC Formal Consulting Services

Turn-Key Projects

For customers who don’t have formal expertise or need additional resources to verify their blocks or IPs.,

What: 

  • Synopsys Formal Consulting Services team takes complete ownership of verifying the pre-selected blocks using VC Formal Apps. 
  • Final delivery includes formal setup, SystemVerilog assertions, any Tcl scripts developed, documentations, the results database with the predefined goals accomplished, as well as knowledge transfer to the customers. 
Formal Audit / Guidance Project - Synopsys VC Formal Consulting Services

Formal Audit/Guidance Project

For customers who have some formal experiences but want to improve their formal methodologies to execute formal signoff on their own in future projects. 

What: 

  • Synopsys Formal Consulting Services team audits existing formal test plans to assess gaps, improve usage, as well as recommend metrics to implement formal signoff strategies. 
  • The team can also work alongside customer engineers on a specific project to guide the engineers in completing the formal verification project. 
Formal Signoff Methodoloty Training - Synopsys VC Formal Consulting Services

Formal Signoff Methodology Training

For customers who are new to formal verification and have decided to add formal to their overall verification flow. 

What: 

  • The training covers advanced topics such as how to write proper constraints, checkers, abstraction models, and scoreboards to achieve signoff.
  • Users will gain comprehensive knowledge on how to use different formal technologies effectively and efficiently to achieve formal signoff. 

What Our Customers Are Saying About VC Formal

"VC Formal’s HECTOR technology delivers best-in-class performance and quality of results, which enabled us to successfully reduce our simulation efforts and helped catch more than 30 RTL bugs in our design."

Xiushan Feng
Formal Verification Lead for GPU & CPU, Samsung

"The newly introduced VC Formal Regression Mode Accelerator app consistently delivered an order-of-magnitude performance improvement along with improved convergence of additional inconclusive properties for the most complex SystemVerilog Assertions on our design blocks."

David Vincenzoni
R&D Design Manager, STMicroelectronics

"To efficiently perform comprehensive verification of these complex SoCs, static, dynamic and formal verification is required. With VC Formal and Certitude's fault injection and mutation technology, we addressed a potential problem for a specific bus access timing scenario in our past MFP products. By using a CPU model that could synthesize the logic with VC Formal, we also proved that the issue would not occur under the use conditions of the product. This enabled us to enhance the verification quality of our products and shorten time to market."

Motohide Murao

General Manager of Software 1 R&D Division, Kyocera Document Solution Inc.

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